VPX moduleCurtiss-Wright Controls Defense Solutions (CWCDS) has introduced the CHAMP-WB (“WideBand”), said to be the Industry’s first Xilinx Virtex-7 OpenVPX COTS DSP Engine designed for sense-and-response applications that require high bandwidth and minimal latency. In addition, the company is introducing its first module for the CHAMP-WB, the TADF-4300, featuring Tektronix Component Solutions’ 12.5 GS/s Analog-to-Digital (ADC) and /Digital-to-Analog (DAC) technologies. Combined, these two modules form the CHAMP-WB-DRFM and are asserted to provide the highest bandwidth/highest resolution platform for wideband Digital Radio Frequency Memory (DRFM) processing available in the embedded defense and aerospace market, delivering 12.5 GS/s 8-bit ADC and 12.5 GS/s 10-bit DAC performance from a single 6U slot. The CHAMP-WB-DRFM card set is optimized for EW applications and provides according to the company, the industry’s lowest latency, highest performance ADC/DAC performance and highest available I/O bandwidth. Based on Tektronix’s silicon germanium (SiGe) based data converters, the TADF-4300, when coupled with the CHAMP-WB’s on-board Virtex7 FPGA and high-speed wideband interfaces, is said to enable designers to develop embedded DRFM solutions with 3x the performance of existing CMOS-based offerings.

As a standalone card, the CHAMP-WB is designed to support any application that needs large amounts of I/O bandwidth coupled with significant FPGA processing and minimal delay. Its modular design supports both standard Virtex 7 -compatible FMC (VITA 57) mezzanine cards as well as providing for higher throughput modules such as the TADF-4300.  These cards support commercial applications such as direct RF digitization, ground-penetrating radar (GPR) and coherent optical applications, as well as enabling deployed defense and aerospace, sense & response applications that require wideband capability and low latency, such as DRFM, EW, Signal Intelligence (SIGINT), and Electronic Counter Measures (ECM).

In addition to operating as a 12.5 GS/s ADC/DAC unit the TADF-4300 module can also operate in a dual-channel 6.25 GS/s ADC-only or DAC-only mode.  The module contains built-in clock generation and calibration logic for maintaining optimal performance in different environments and over temperature.

The CHAMP-WB couples the dense processing resources of a single large Virtex7 FPGA with two high-bandwidth enhanced FMC mezzanine sites on a rugged 6U OpenVPX (VITA 65) form factor module. The board’s data plane connects directly to the FPGA with support for Gen2 Serial RapidIO (SRIO) data plane fabric. Alternate fabrics can also be supported with different FPGA cores. A Gen3 PCI Express (PCIe) switch connected to the board’s expansion plane enables a single host card, such as Curtiss-Wright’s VPX6-1957 or CHAMP-AV8 to control multiple CHAMP-WB cards without utilizing data-plane bandwidth.

Memory support on the CHAMP-WB includes two (2) 64-bit 4 GB DDR3L memory banks that provide up to 8 GB of on-card data capture or pattern generation capability.

The CHAMP-WB features two (2) high-bandwidth FMC sites that have been enhanced with an auxiliary connector to provide additional I/O capability. Twenty back-plane SERDES links, which can operate up to 10.3 Gbps, and 16 LVDS pairs provide additional I/O capability.
The TADF-4300 module supports sampling in the 2nd nyquist zone, to analyze signals up to 8 GHz and provides sub-30 ns latency for the ADC and sub 10ns for the DAC.  Spurious Free Dynamic Range varies over frequency, and is >58 dB up to 3 GHz and decreases to 45 dB from 3 GHz to 6 GHz signal input frequency. ENOB varies linearly from 7.2 at low frequency, 6.5 at 3 GHz and 6.2 at 6 GHz.

The CHAMP-WB, the newest addition to Curtiss-Wright’s HPEC (High Performance Embedded Computing) product family, and the TADF-4300 module complement Curtiss-Wright’s wide range of Intel and Power Architecture-based VME and VPX SBCs, DSP engines and GP-GPU engines, such as the VPX6-1957, and CHAMP-AV8, as well as Curtiss-Wright’s broad range of signal processing I/O FMC mezzanine products including  the FMC-516/518.  Combining these products with Curtiss-Wright’s switch and backplane products enables system designers to quickly and easily develop interoperable highly scalable, high performance systems.

CHAMP-WB Performance Features:

•    OpenVPX (VITA 65) profile MOD6-PAY-4FIQ2U2T-12.2.1-1: VITA 48 1” pitch format
•    VPX REDI (VITA 48 option)
•    User-programmable Xilinx Virtex-7 FPGA (X690T or X980T)
•    8 GB DDR3L SDRAM in two banks
•    Four (4) 4-lane serial data plane links to the backplane
•    Up to 10.3 Gbps data rates
•    Gen2 SRIO
•    One (1) 4-lane Gen3 PCIe connection to onboard Gen3 PCIe switch
•    16 LVDS pairs to the backplane
•    Two (2) enhanced FMC (VITA 57) mezzanine sites with 128 differential signal pairs
•    Site #1 supports JESD204B FMCs with up to 8 serial links
•    Site #2 has optional support for up to 160 LVDS pairs with X690T FPGA
•    Two (2) 8-lane expansion plane fabric ports to the backplane
•    Configurable NTB support
•    Thermal sensors for monitoring board temperatures
•    Sensors for monitoring board power consumption
•    Support for ChipScope™ Pro and JTAG processor debug interfaces
•    Backplane clock/sync paths to mezzanines sites
•    VITA67.2 backplane option
•    Ruggedization levels supported range from Air-cooled Level 0 (commercial) to Conduction-cooled Level 200 (future)
TADF-4300 Performance Features:

•    Features Tektronix ADC/DAC technologies to support high resolution, high bandwidth signal acquisition and generation
•    Double-wide enhanced FMC module
•    12.5 GS/s 8-bit Analog-to-Digital Converter
•    12.5 GS/s 10-bit Digital-to-Analog Converter
•    Onboard, programmable sample clock
•    Onboard calibration
•    External reference clock input to support multi-channel synchronization
•    Streaming interface to host FPGA for continuous full-rate acquisition applications
•    Air-cooled and Conduction-cooled

Curtiss Wright Controls Defense Solutions,