ChipX announced the introduction of Hybrid ASIC, the implementation of a structured ASIC as IP on a Standard Cell device. This development approach is said to allow for rapid and economical product line development and save companies recurring engineering (NRE) and tooling costs. According to the company, turnaround time for logic changes can be as short as six weeks, from tape-out to packaged and tested prototypes with NREs starting as low as $99,000 in 0.13µ. Typical applications for Hybrid ASIC include video compression or data encryption for designers who wish to implement the same device with different compression or encryption schemes. The implementation of an ASIC with a pre-standard interface or algorithm is also appropriate for Hybrid ASIC. In these cases, the potentially variable design logic is placed in the configurable structured ASIC area. A proliferation of new products can be built by changing just the design in this area, without requiring additional work on the fixed portions of the design.