Providing hitless reference and master/slave switching support with a SyncLink cross-couple data link, Connor-Winfield’s STC5230 synchronous clock IC uses 2 independent timing generators, T0 and T4, that include a digital phase-locked loop (DPLL) in Freerun, Synchronized, and Holdover modes with programmable loop bandwidth of each DPLL from 90 mHz to 107 Hz. The ITU-G.813- and Telcordia GR1244 and GR253-compliant components accepts 12 automatically-detected individually-monitored reference inputs, and generates 9 independently-synchronized output clocks. The TQ100-packaged chip offers phase delay compensation in 0.1 ns steps up to 409.5 ns, field upgrade capability via SPI bus interface or optional external EEPROM, IEEE 1149.1 JTAG boundary scan and operation with an external OCXO or TCXO as its MCLK at 20 MHz. The device exhibits phase rebuild on re-lock and reference switches, and support for manual and automatic reference selection in SDH SETS, SONET Stratum 3, 4E, 4 and SMC, and Synchronous Ethernet applications. Pricing is $40.
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