CHiL Semiconductor Corporation announced a new configuration in its computing voltage regulator (VR) solutions for CPU, GPU, and DDR applications. Now configured to optimize efficiency from the lowest idle state to the highest operating state of today’s high performance server, graphics and desktop solutions, CHiL asserts its next generation true-digital power algorithms have increased efficiency up to 15 percent, especially at low loads.
When applied to server class products, CHiL’s efficiency-improving techniques can save up to 85 W per server card at peak operation, and 40 W during typical operation, according to the company. In data centers that operate 24/7, this is said to translate to annual savings of 350 to 700 kWh per board.
Throughout the entire operating range, the company’s variable gate drive algorithm adjusts the gate drive voltage to minimize gate drive losses at low operating loads, and optimize conduction losses at high loads.
In idle state, CHiL’s proprietary discontinuous-mode operation requires no sensing circuitry and can be configured digitally to optimize performance. In low current modes, the automatic dynamic phase control optimizes the number of operation phases to minimize power losses. Simultaneously, the non-linear digital transient response, known as adaptive transient algorithm, or ATA, can easily respond to the processor, instantly increasing its load.
CHiL true-digital algorithms can be applied to readily available off-the-shelf components, and do not rely on specific, often costly, semiconductor products to achieve these exceptional power savings.