IEEE Std. 1149.1, or more commonly known as Boundary Scan, is a specification for testing the inter connectivity of components on printed circuit boards. The standard was formed by a consortium of companies known as the Joint Test Access Group or JTAG in 1990. As more functionality is being packed into smaller circuit board footprints, the space for test points is being squeezed out. The standard defines test methods to address the loss of test coverage from the increasing loss of test access on circuit boards
Since its standardization, boundary scan can be found on many components that are used in many of today’s electronic products around the world. The mass adoption has expanded the application of the standard to include functional test, built-in self test as well as analog test. Boundary scan is gradually becoming the most common test method for testing digital components and circuits.
Advantages of Boundary Scan Testing
The major advantage of boundary scan is that it enables test coverage at the in-circuit test stations in limited test access situations. This is mainly facilitated by the test cells that are designed into the integrated circuits (IC) as part of the standard. The test cells can be controlled to drive or receive signals from the connected nodes on the circuit board without the need for test points. The cells are linked together such that the tests executed during a boundary scan test do not need to pass through the core logic of the IC. This effectively eliminates the need for test engineers to fully understand the functions of the IC in order to drive stimulus signals through the IC to test the pins of the component. The result, shorter test development times. Another major advantage is from the standardization of the test method. Since it is a standard, boundary scan tests can be generated automatically, reducing the effort to add test coverage to the printed circuit boards.
Issues with Boundary Scan Test Implementation
The use of test cells also causes one of the issues of implementing boundary scan tests. Many of the issues seen with boundary scan test implementation are design related. Both the component design and circuit design can contribute to these issues. Even now, test engineers get boundary scan description language (BSDL) files which do not correctly describe the boundary scan design, especially the test cells, on the IC. This consequently results in erroneous tests developed and hours of debug as the test engineer assumes that the test was correct. Currently, there are tools on the web for users to check the syntax of the BSDL files. However, to check if the BSDL describes the boundary scan design correctly, requires actual electrical testing. This can be done at the In-Circuit tester. The validation process requires exercising the input and output pins to determine if their behavior matches the description in the BSDL file.
Enabling Boundary Scan Test
In circuit designs, the following are some suggestions to enable easier boundary scan test implementation for the printed circuit board assembly.
Pull-up or Pull-down resistors for Test Access Port (TAP)
It is very important for the TCK, TMS, TDI, TDO and TRST pins to be pulled up or pulled down by resistors during a boundary scan test. The resistors are there to prevent the IC from inadvertently entering into boundary scan mode or changing of states during a boundary scan test. In most cases, there are weak pull-ups and pull-downs designed into the IC, but external pull-ups and pull-downs are recommended. The recommended configuration is to pull up TDI, TDO, TMS and TRST with a 1.2-kOhm (typical) resistor to Vcc and pull down TCK with a 100-Ohm resistor to ground. Users may refer to the IC design document for recommended resistance values from the IC designer. The values of the pull-up or pull-down resistors may impact the overall power consumption. For example, lower pull-up or pull-down resistances require stronger external driver capabilities.
Chaining-up Boundary Scan Devices for Better Test Coverage and Easier Debug
Connect the TAP of each boundary scan IC into a daisy chain with the TDO of the first IC connecting to the TDI of the second IC, the TDO of the second IC connecting to the TDI of the third IC, and so on. The TMS and TCK ports are all shorted together with the traces running in parallel. It is important to design the TDI pin away from the TDO pin to avoid possible short circuit between the two. For long chains, the fan-out of the TCK and TMS need to be considered. Buffer circuitry could be placed within the chain to boost the signal across the chain. The order of the ICs within the chain is mostly determine by the location of the ICs. Where possible, place new and unverified boundary scan ICs at the ends of the chain. This is to ensure that these components can be easily removed from the chain if necessary.
Chaining the boundary scan ICs together allows test signals to be passed between boundary scan ICs via the test cells (See (A) in Figure 2). The tester does not need to drive or receive signals directly from these nodes; therefore, test points are not required.
Test Access Where Needed
Since the function of the boundary scan component is controlled by the TAP, it is critical that each TAP pin has a test point assigned. Without which, it is not possible to test the component using boundary scan. Where possible, assign probes on the TDI-TDO connections between the boundary scan ICs (See (B) in Figure 3). These probes can be used to help improve the debug process by isolating the ICs that are difficult to debug from the chain. For the other pins on the boundary scan component, there should be at least one test point assigned. This is to validate that the component can be put into boundary scan mode and able to output correct signals (See (C) in Fig3). For certain boundary scan ICs, a number of pins (less than five pins) need to be activated in order to put the IC into boundary scan mode. These pins are called compliance-enable pins, and they would require test access on each of them. The boundary scan standard includes syntax to add warning messages into the boundary scan description language (BSDL) file. The message could warn users of the need to use the compliance-enable pins for boundary scan testing.
Using Level Shifters Between ICs of Different Logic Levels
Depending on the circuit design, there may be boundary scan ICs with TAPs of different logic levels that have to be connected together in a chain. Level Shifters need to be added to the chain between these ICs to manage the different logic levels.
“Quiet” The board Under Test
The circuit surrounding the boundary scan device under test should be “quiet” and not be “noisy” with an uncontrollable signal. Since boundary scan testing uses the test cells within the boundary scan IC to drive signals around the board, the drive current may not be strong enough to over-drive other active components on the board. This could cause unpredictable results in testing when there is a “noisy” active signal on the board. To resolve this, test access and a series resistor to the enable pins of these components should be designed into the circuit so that the the “noisy” components can be disabled by putting the outputs into a tri-state mode or inputs into a don’t-care mode.
As ICs become more complex and printed circuit boards shrink further in size, we will continue to see a gradual increase in importance of boundary scan test. Easing boundary scan into in-circuit testing starts from the component and printed circuit board designs, to the automatic generation of tests and debug tools. Designers and test engineers should work closer together to get this going.