Tips for a More Robust Power Supply Design: Avoiding EOS
by Alexander Craig, Fairchild Semiconductor, www.fairchildsemi.com 
Failures of semiconductor ICs are typically due to overvoltage or overcurrent for a given junction temperature. This overvoltage can be caused by an external factor or an uncontrolled switching inductance. The overcurrent failure can be caused by excess junction temperature due to excessive power losses and a poor thermal path or an abnormal load current. It is typical for a failure report to state Electrical Over Stress(EOS). The key to avoiding EOS is to identify which hazards your design will likely experience and design accordingly. Typical hazards are heat, abnormal input voltages and abnormal load conditions.
To avoid abnormal input voltage hazards, you need to select devices with a breakdown voltage 20-25% higher than you expect to see in the application. Be mindful of any uncontrolled switching inductance (V=-L*di/dt). This unclamped inductance is the cause of the majority of overvoltage failures.
To avoid thermal issues, you need to choose devices based on Pd (Power dissipation) and R?ja (thermal resistance junction to ambient) calculations. The basic calculation is junction temperature (Tj), Tj=Pd*R?ja +Ta, R?ja = R?jc + R?ca. R?jc (thermal resistance junction to case) can be improved with new packages like the Power56 package. Low power dissipation may be achieved by selecting lower conduction loss devices like the PowerTrench MOSFETs for lower voltages or SuperFETs for high voltage applications. Optimizing switching losses can be achieved by designing soft switching LLC resonant converters with devices like the FSFR2100 or Quasi-Resonant operated flyback devices like the FSQ0765R that have overcurrent and thermal protection features that are built-in.
To avoid abnormal failures caused by load abnormal conditions, you need to design your supply with overload and current protection in conjunction by selecting devices with enough thermal head room to survive the load stress until the control circuit can respond. Some control ICs like the SG6846A have dual overcurrent set limits and rely heavily on the power devices’ ability to endure the short power pulse that is seen in some applications.
Distributed Architecture Solves Intrusion on the Software Layer
With advances in DSL technologies and with the deployments of FTTB and FTTH, there is a sudden explosion in the amount of raw bandwidth that can now reach every home. Using VDSL2 technology, residences can get over 100 Mbps data rate. With fiber technologies the bandwidth can be as high as Gigabits per second. Service providers all over the world are trying to enable value-added services like voice, video, security and gaming that would efficiently exploit this increase in available bandwidth. At the same time service providers are designing new Residential Gateways that are remotely managed and can be configured and upgraded remotely with newer services once they become available.
Designing Residential Gateways for multiple services, security and manageability can be a challenge. Different services require different throughput, latencies and processing power. Service like voice and gaming are very sensitive to latencies while the management application can be quite tolerant of latencies. Video requires higher throughput and low latencies. Applying security policies and encryption is a very CPU intensive task. Implementing these services on a centralized CPU architecture requires precise allocation of CPU across all of the applications; this could be extremely difficult if not impossible. Adding to the complexity is the fact that operating systems are usually provided by different companies than those developing applications and services. While there are real-time operating systems, effectively utilizing the CPU for all of the applications using the operating system remains a significant challenge. Linux, increasingly being used in embedded application for its rich set of applications, is however very poor in its real-time handling.
Fusiv solves the problems of implementing multiple services and operating system inefficiencies by departing from conventional centralized CPU architecture. Fusiv technology implements a distributed architecture, one in which the data plan is completely separated from the control plane. From the time the packet is received, processed (including applying NAT, Firewall, Security, and QoS policies), and sent out on the outgoing interface, the packet is handled in the data plane. The data plane is designed using programmable engines called accelerator processors. Programmable engines provide the necessary flexibility to tune the data path to meet the requirements of specific software and the protocol stack running on the control plane. Operating system and management software runs on the RISC CPU which is part of the control plane. Since the data plane is isolated from control plane the services are unaffected by the operating system used and their associated inefficiencies. A simple API hides the complexities of the data path and provides an efficient interface for the integration of the operating system, protocol stack and applications running on the main CPU.
Designing Interconnects for Mobile Phones
Interconnections for mobile phones typically include a differing array of connectors to facilitate various component connections, including the headphone, battery charging and antenna functions, to name a few. These applications can often result in uneven spring forces and poor contact resistance.
With the decreasing size of handheld devices, miniature interconnections, incorporating reliable and robust designs, become critical. Equally as important is aggressive component pricing, which remains a key goal in the extremely competitive mobile phone market.
To meet these demands, interconnect solutions for mobile phones must incorporate a variety of design elements, including varying contact heights (such as 1.3mm to 4.0 mm free height), side wings for protection of both the active parts of the contact and to prevent the contact from overstressing, excellent hertz stress, low contact resistance, and robust contact connections. While X-Y-Z movement allows a robust connection between the contact and component assembly, utilizing pre-loading and anti-life design features further enhances the interconnect, allowing some connector contacts to maximize contact force and offer a mating cycle as high as 3000 times.
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