Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next.
At 10nm and beyond, IC vendors are determined to scale the two main parts of the finFET structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects may continue to fall further behind the curve.
In fact, the interconnect issues began to emerge at 20nm or so, and the problems are becoming worse at each node. Interconnects—the tiny copper wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.
“RC delay (is) the delay in signal speed through the circuit,” said Rajkumar Jakkaraju, product manager for the Metal Deposition Products Business Unit at Applied Materials, in a recent blog. “RC delay is important because it can become a significant obstacle to continue downward scaling of logic and memory devices that drive the performance of today’s multi-functional, mobile consumer electronic devices.”
In a chip, the average delay due to copper resistivity increased by 7.6% from 45nm to 22nm, according to a recent study from the Georgia Institute of Technology. But the average delay is expected to reach 21.8% from 22nm to 11nm, and by 48% from 11nm to 7nm, according to Georgia Tech.
Over the years, the industry has developed and proposed several solutions to solve the bottleneck in the interconnect. For example, the momentum is building for new materials in the metallization scheme, such as cobalt (Co) and ruthenium (Ru). In addition, a breakthrough technology called air gaps is entering the picture.
But still, the rate of progress and change remains slow amid a slew of challenges in the arena. “That’s the grand challenge,” said Mark Rodder, senior vice president of the Advanced Logic Lab at Samsung. “We really need a breakthrough in the interconnect.”
Needless to say, foundry vendors and their customers need to keep tabs on the progress of the interconnect. So, Semiconductor Engineering has a taken a look at the status of the interconnect, the difficult process steps, and what’s ahead.