The cost comparison between 3D-SIC [vias middle ( 5 x 50 um)] vs 3D-WLP [vias last (backside) (35 x 50 um)] Cu filled TSV  is shown in the fig below at a volume of 150K 200 mm wafers/yr. All the processing costs are normalized to the cost of “Cu-Cu Bonding” step. Processing of the 3D-WLP vias requires two steps of silicon etching – the first for polymer deposition and the second for plating. The process time is therefore longer which results at a higher TSV processing cost.

When 3D-SIC TSVs are used, backside processing includes thinning of the top wafer and exposure of the bottom end of the through-silicon-vias. A passivation layer is deposited on the backside of the wafer and 3D bonding can be achieved using copper-copper (Cu-Cu) thermo-compression between the exposed TSVs and the landing pads of the bottom layer. Therefore, the cost of backside processing includes only the thinning, TSV exposure, and passivation steps and it is shown below. Alternatively, the bonding between the top and bottom stacked layers can be done using copper-tin (Cu-Sn) microbumps.

In this case, the microbumps are created on top of the exposed TSVs at the backside of the top layer. The location of the microbumps can be moved away from the exposed TSVs, if necessary, using a re-distribution layer (RDL). The cost contribution of backside processing using Cu- Sn microbumps or Cu-Sn microbumps and RDL.

When 3D-WLP TSVs are used, thinning of the wafer is done prior to the formation of the TSVs. The option of Cu-Cu thermo-compression is not available for 3D-WLP vias. Instead a Cu-Sn microbump is created on top of the TSV by extending the TSV plating process. A re-distribution layer may also be

used if necessary. The cost for these processes is similar to the corresponding backside processing cost for 3D-SIC TSVs, shown in the figure below.

When looking at the stacking process itself (at assumed equal yield) , both Cu-Cu bonding and Cu-Sn bonding are examined in both W2W and D2W processes. Collective bonding between the two layers is done in both cases in a single step. In the case of D2W stacking, the top layer wafer is diced and chips are individually picked and placed on the top of the bottom layer wafer. Then the bottom wafer

is also diced to separate the stacks. Cu-Sn bonding requires shorter processing times when compared to

Cu-Cu bonding, therefore resulting at a lower processing cost.


Of great interest is the IMEC plot of processing cost (etch, liner, barrier, plate) vs TSV depth. TSV depth and diameter affect the processing time of the steps required for TSV formation. In addition, the

TSV diameter and minimum pitch affect the total area of a chip, the number of chips on a wafer, and eventually the cost of a 3D stack. Increasing the depth of a TSV affects the time for etching, liner

and barrier deposition, and plating steps. Therefore, the cost of TSV processing is increasing with TSV depth as illustrated in the figure below. One can see that 50 um TSV will cost 50%  vs 200 um TSV. 


As shown in the figure below, the lower integration density of the 3D-WLP TSVs makes the cost of this integration scheme prohibitive for a large number of vertical interconnects. In addition the lower stacking yield of the W2W stacking strategy results in a higher system cost for both the 3D-SIC and the 3D-WLP implementation schemes.


It is generally accepted that redundancy / repair schemes will be required to yield parts for commercialization. IMEC has examined the cost that this will result in for 1K, 10K and 100K TSV per stack 3D-SIC vs 3D-WLP. As shown below using TSV tripling results in a 16% cost increase for a 100K / stack  3D-SIC  solution and an unacceptable 250+% increase in cost for 100K / stack for the lower density 3D-WLP solution.


Yole Développement TSV CoSim Cost Model

Another cost model option is the Yole Développement (Yole) model,  “TSV CoSim” which is not limited to IMEC process flows. The cost model engine accesses two regularly updated databases, one containing all known pieces of equipment, the other containing materials. Each piece of equipment is set with default price and technical feature values, which can be overridden by the user.

These 2 models (IMEC’s and Yole’s) now offer most companies the opportunity to cross-check simulations and confirm the effect of any investment or manufacturing assumption for any application targeting Through Silicon Vias. For further information on the models contact IMEC and Yole Developpement respectively.