Solar micro inverters are an emerging segment of the solar power industry. Rather than linking all solar panels in a solar installation through a central inverter, solar micro inverter systems instead place smaller, or “micro,” inverters in line with each individual solar panel. While solar micro inverters yield many benefits, including elimination of partial shading conditions, increased system efficiency, improved reliability and greater modularity, they can be extremely challenging for designers. They require the controller to use complex algorithms to control the power stage, synchronize with the grid using software phase locked loop (SPLL) and track to the maximum power point of the panel, along with executing complex state machines, which increases the computational load on the processor. This article explains embedded challenges in control of solar micro inverters and provides insight into power stage design and control.

The solar panel, or photovoltaic (PV) panel as it’s more commonly called, is a DC source with nonlinear voltage (V) versus current (I) characteristics. The key challenges in PV inverter system design are to extract maximum power from the panel by operating the panel at the maximum power point (MPP), and to convert the power efficiently to feed a clean current into the grid. A typical PV grid tied inverter consists of a string of PV panels tied together to a single inverter stage; these are called string inverters. However, these systems are not able to track to the MPP under partial shading conditions, hence care and planning is needed when installing these. An emerging paradigm involves inverters dedicated to individual PV panel, also called micro inverters, which relaxes the constraints on installation and as dedicated MPP tracking (MPPT) can be performed, the system efficiency increases.

Solar micro inverter hardware design
Typical panels provide ~20-40V output. To feed current into the grid, this voltage must be boosted to ~320-400V and then inverted to feed current into the grid. Thus a typical micro inverter has two stages: a DC-DC stage and a DC-AC stage, as shown in Figure 1.

Figure 1. PV grid-tied inverter

Many solutions are available to aid solar power designs. One of these specifically for those relying on solar micro inverters is the C2000 Solar Micro Inverter Development Kit from Texas Instruments (TI). A high gain clamped flyback stage, switching at 100 KHz, is used on this kit to reduce the voltage stresses on the MOSFETs. Due to the high gain, the PWM resolution is reduced ), whereas the ADC resolution remains the same (). To avoid limit cycle behavior, the resolution of the PWM must be greater than the ADC, hence TI’s C2000 Piccolo TMS320F28035 microcontroller (MCU) integrates a high-resolution PWM module, which enables effective number of bits to be more than what the CPU clock can provide for the given switching frequency. Additionally, utility requirements mandate isolation of the panel from the grid. Transformation size is inversely related to the frequency of operation, hence a compact isolation of the panel from the grid is achieved using the high frequency transformer. Figure 2 shows a schematic of the power stages on a solar micro inverter.

Figure 2. Solar Micro Inverter Development Kit power stage diagram

A grid clamped inverter stage is used to connect to the grid to avoid issues with ground current faults. The switched current from the inverter is filtered using an output filter. The design of the filter is critical as it affects the quality of the current injected into the grid. An inductor (L), inductor capacitor (LC) or inductor capacitor inductor (LCL) filter can be used to achieve this. LCL filter is preferred as it can be used with a small size output filter; however, it increases the complexity of the control because the LCL filter has inherent resonance. The resonance can be detrimental in the stability of the inverter and must be damped. Passive damping, by adding power resistors, results in reduced efficiency and active damping solutions involve using additional sensors such as capacitor current which increase system cost. Alternatively, a complex pole zero pair in the compensator can be used to damp the resonance. Relative to passive damping, this increases the compensator complexity, but as modern MCUs can tackle this, reduction of the output filter size is preferred.

Control and software design
Implementing the control loops of multiple power stages, as well as executing the algorithms needed for grid connection and MPPT can consume significant CPU bandwidth. TI’s C2000 MCU solar software library has optimized functions (assembly optimized where applicable) available for executing the key blocks used the PV inverter control in fixed- and floating-point math. The blocks include adjustable notch filter, which is used to eliminate any effect of AC power ripple on the control variables. Compensators such as 2p2z and 3p3z compute the effort based on reference and feedback, and software phase locked loop locks in the grid phase, MPPT algorithm and power monitoring. In addition to the control loops, a state machine also needs to be implemented to start the inverter. Figure 3 shows the high-level control diagram of a solar micro inverter.

Figure 3. Control diagram of a PV micro inverter

The goal of the PV inverter is to feed a clean current into the grid. To do this, the current compensator must be designed with a high bandwidth. Figure 4 shows the current control diagram for a grid connected inverter.

Figure 4. Feedback linearization for inverter current control loop

Figure 4 demonstrates that the current compensator loop is subject to disturbance due to grid voltage variations and a typical PI compensator is unable to track to the reference current with zero steady state error. Hence effects of the grid voltage disturbance must be taken into account. This is achieved by first assuming the current compensator bandwidth is much higher than the grid voltage frequency and linearizing the feedback. Thus the current compensator is thought of as generating the reference across the LCL filter and the actual duty cycle computed for the inverter voltage using the formula:

Where D is the inverter duty cycle, VDC the DC bus voltage, VG is the grid voltage, i*g is the inverter current reference, ig is the inverter current reference, VLCL is the voltage across the LCL filter, Gp is the plant model of the LCL filter, Gc is the current compensator used and vi is the averaged inverter output voltage.

Conclusion and results
Figure 5 shows the frequency response of the closed current loop, which highlights the damping of the LCL filter and the high bandwidth feasible because of the feedback linearization.

Figure 5. Closed loop inverter current frequency response                                                                                         

Figure 6(a) shows steady state voltage and current of the micro inverter and highlights good power factor achieved and THD. Figure 6(b) shows the starting and stopping sequence of the inverter by displaying the inverter current and panel current as the micro inverter sequences through the state machine.

Figure 6 (a) Steady state inverter voltage and current (b) inverter stop, start and MPPT tracking

Solar inverter designs can be a challenge, but this article has presented reasons for power stage selection, the need for high-resolution PWM for a high gain DC-DC stage, a solution to complexity in grid current control using feedback linearization, and an illustration of a complete control scheme for a solar micro inverter to help mitigate these challenges.