Portable devices such as cell phones, MP3 players and tablets have become popular over the years. Most people own at least two of these devices. Each device requires a power adapter to charge and provide power for these portable electronics. However, when these adapters are left plugged into the wall socket, idle, not supplying power or charging a device, they are still dissipating power and wasting unnecessary energy. To save energy, owners would be wise to unplug their adapters. However, due to convenience some owners leave these devices idly plugged into the wall, even when not in use.
The US Department of Energy (DOE) is aware of the energy wasted by idle adapters and is cracking down on it. They are generating legislation to limit the maximum amount of input power when an adapter is left idle. The latest requirement is that external power supplies/adapters used for portable devices in the US designed for 50 W or less will dissipate no more than 100 mW when they are left in idle. Most adapters for these portable devices fall in this category and are designed with inexpensive flyback power converters. This article discusses techniques the power supply designer can use to reduce idle power loss in these designs, and how a quasi-resonant/discontinuous mode flyback converter with a special control scheme can meet this no-load input power requirement. See Figure 1 for a functional schematic of such an offline flyback converter.
To reduce idle power losses, a few design techniques can be used. First you can remove the trickle charge resistor (RT) startup scheme (Figure 1). To show how much power this resistor could dissipate, let’s look to see what happens if the designer uses a trickle charge startup scheme and choses 1 M-Ohm resistance for RT. This resistor dissipates roughly 26 mW at 115 V rms input, or 26 percent of the allowable power dissipation allowed by the DOE, and could cause the design to fail the idle input power requirement of 100 mW (Equation 1).
The idle power loss caused by the trickle charge resistor can be removed with the circuitry presented in Figure 2. This circuitry provides power to the flyback controller (VDD) while capacitor C1 is energizing during startup. Eventually C1 will develop a voltage potential that is large enough, where it forces the shunt regulator (TL431) to turn off transistor Q1. This circuitry removes the unnecessary power losses caused by the trickle charge resistor (PRT). This circuitry provides VDD with roughly 10V of bias voltage for about 100 ms before turning off Q1. Since the designs for these adapters are so cost sensitive, a designer may not want to add all of this additional circuitry. The good news for these designs is that there are a few flyback controllers on the market today that have built-in green boot-strap circuitry, just to remove this significant unnecessary idle power loss.
The second technique that could be used is to choose a flyback controller that does not require a secondary side feedback circuitry that uses a constant voltage, constant current controller. The controller in Figure 1 uses an auxiliary winding off of T1 to indirectly sense the output voltage (VS) through the transformer turns ratio of T1, instead of an opto isolator error signal feedback circuitry. The opto-isolator feedback circuitry, if used, can require up to 1 mA of bias current from the output to operate correctly. In a 5-V adapter application this dissipates roughly 5 mW of power, which is 5 percent of the allowable idle output power. Removing this idle power loss makes it easier to achieve the no-load input power requirements. Also, removing the opto-feedback circuitry reduces the design’s overall component count and cost.
To help meet idle input power requirements, a control technique for flyback converters called primary side regulation (PSR) can be used. The controllers in this example use a combination of frequency modulation (FM) and primary peak current (IPPK) amplitude modulation (AM) to control the duty cycle of the quasi resonant/discontinuous flyback converter, reducing switching losses. Figure 3 shows a functional schematic for this type of flyback controller.
Figure 4 describes the frequency (fs) and IPPK current modulation by the Texas Instruments UCC28711 constant voltage/constant current flyback controller based on changes at the controller’s voltage error amplifier (VEA) output. When the converter requires maximum duty cycle it is operating at the maximum switching frequency (100 kHz), and the flyback is operating as a quasi-resonant flyback converter. As less duty cycle is required VEA output decreases and a voltage-controlled oscillator decreases the converter switching frequency, running the converter deeper into discontinuous mode. Decreasing the switching frequency as the load decreases also decreases the power converter’s switching losses (PSW).
To avoid audible noise when the VEA operates between 3.35 V and 2.2 V, the controller operates at fixed frequency of 33 kHz and adjusts the converter’s duty cycle by linearly modulating the amplitude IPPK. The amplitude of IPPK in this fixed frequency operation is linearly adjusted down from its peak value to one-fourth its peak value. This decreases the energy stored in the transformer, and decreases the amount of energy available to produce audible noise at switching frequencies below 25 kHz in the audible range. As the converter demands lower and lower duty cycles, where VEA output drops below 2.2V, the controller once again decreases the switching frequency all the way down to 680 Hz, reducing the idle power switching losses.
Equation 2 describes the switching losses of the FET QA (PSW(FS)) in a quasi-resonant flyback converter. IDS is the FETs peak drain to source current, where VDS is the voltage across the FET just before being turned on. COSS is the FETs average drain to source capacitance. VG is the voltage level that drives the FET, and QG is the gate charge at VG. Variable tR is the rise time of the FETs drain to source voltage when the FET is turned off. From observation, this equation confirms that decreasing the frequency reduces FET switching losses. When the converter is idle and operating around 680 Hz, the FET’s switching power losses are more than 100 times smaller than when operating at the 100 kHz switching frequency.
Using the design techniques presented in this article, a 5-W USB adapter evaluation module was designed and tested . This evaluation module dissipates less than 10 mW of input power in the idle state at 115 V/230 V rms input voltage, easily meeting the DOE idle power requirements. This was achieved by having a green/active boot strap circuit internal to the control IC that was similar to that presented in Figure 2, which only dissipates/applies power to the controller during startup and turning off once the bias winding of the transformer could deliver energy to power the control IC. This was also accomplished with a discontinuous current-mode flyback controller using a voltage-controlled oscillator to decrease the converter’s switching frequency/duty cycle at lighter/idle loads, thus, decreasing the power converter’s switching losses when the adapter is in an idle state.
* Download the UCC28711EVM-160, 5W USB EVM.
* Download the datasheet for the UCC28711.