While most designs using High Reliability MOSFETS are straightforward, there are a few problems that can arise during the design and debug cycle that need to be well understood. These are often difficult to pinpoint. Mysterious problems can occur when shifting to a higher switching frequency or they can occur when shifting to a lower switching frequency and slower rise and fall times at the device. There can also be instances in a half bridge where the turn on of one device, either on the high or low side, attempts to turn on the other respective device in the pair. I’d like to take you through some of these nuances and offer some suggestions for things to avoid.
To understand the Spirito Effect, we need to look at the SOA of a typical MOSFET. This curve is always included in the datasheet for a given MOSFET. The axes are easy enough. Vds on the horizontal axis, Id on the vertical axis. The plot is a log/log plot. The family of curves represents various time durations for a single pulse event. The time durations decrease as pulse power increases. The high current low voltage portion of the curve has a positive slope of unity. What this means is that this is the constant resistance or Rdson limited portion of the curve. Once Vds is large enough, the curves change slope to a constant power model or a slope of negative one. And as we are taught in device physics, this is all that is needed. But it’s not. The distant cousin to the MOSFET, the minority carrier operated Bipolar Junction Transistor has a region on the right hand side of the SOA curve known as second breakdown. Essentially this occurs at high voltage and low current and limits the right extreme of the curve to something less than the constant power than we’d expect to see. Some MOSFETS have a similar portion of the curve. Why some? It turns out that this is technology dependent. Large cell pitch planar or lateral MOSFETS are well spread out. Each cell has an easy means to get rid of any localized heating. Further, the gains of these devices are typically less compared to a trench or super junction device architecture. Trench and super junction architectures also use a tighter cell pitch.
Planar and lateral MOSFETS tend to be stable in linear operating mode or lengthy switching transitions. Trench devices tend to have a reduced power handling in linear mode at higher voltages. Some are sharply reduced. What causes this is pretty straightforward. All MOSFET processes go through great pains in geometry, metallization and layout to guarantee that the gates of each cell are at the same voltage. Similar for the Source metallization of each cell. The drain of course is the substrate so that’s very well shared. The devices are often built with gate charge in mind so the features in the gate and or trench are very uniform from cell to cell. The one thing that is not uniform as a result of this is gain. In linear mode, at lower currents and higher voltages, this slight non-uniformity in cell gain can cause one cell to dominate the current flow. The cell then gets hot, the threshold drops and the cell handles more and more current. In a tight cell pitch structure, this causes a hotspot that can lead to device failure. This is why the trench and super junction technologies don’t fare well in linear mode at high voltage and low current. This is similar to second breakdown in a BJT. The researcher that identified this was named Spirito, and thereby this is known as the Spirito Effect. If you compare datasheets for different parts with similar Rdson and Vds rating, you will see that some devices are much better suited for linear mode operation. They exhibit minimal Spirito effect. These are typically planar devices with larger cell pitch.
The easiest means to map the Spirito effect for any MOSFET on the bench is to look at the temperature coefficient in linear mode. First, set up a given MOSFET with a constant Vgs, similar to that used in your linear circuit and measure Id. Then simply heat the device or observe under self-heating. As the device warms up, the drain current should drop. This is a sure fire indicator that the device is NOT in thermal run-away. If you observe the opposite effect, which is to say that current increases with temperature, this will be problematic in linear mode. As validation beyond the SOA curves, this simple trick is fairly useful for linear mode analysis
When the device is saturated, the gain doesn’t matter. Each cell is at Rdson. The Spirito effect is NOT a problem at saturation. Saturated channel behaves with the positive temperature coefficient that we’d all expect to see
Cdv/dt turn on, coupling through Crss
We know that there are capacitances associated with each MOSFET in play. Coss is the output capacitance, as seen looking at the Drain with respect to the Source. Ciss is the input capacitance as seen looking at the Gate wrt the Source. And the world certainly wouldn’t be complete without Crss, that of Gate with respect to the Drain. Most MOSFETS will have a small Coss, perhaps on the order of a couple hundred pF. Most MOSFETS will have a large Ciss, perhaps something on the order of a couple thousand pF. Crss varies by process, voltage rating and technology. If Crss is large enough AND the rising voltage across Vds at MOSFET turn off is fast enough, Crss can couple enough charge into Ciss to turn the MOSFET on. There are a few ways to mitigate this. Keeping the gate driver circuitry as near the MOSFET as possible and using a lower value gate resistor will resolve this problem in most cases, however I have seen a lot of customers place a small value capacitor in parallel to the GS terminals to add some capacitance to the low side of this capacitive voltage divider, thereby dropping the voltage coupled in.
Reverse recovery of body diode
The intrinsic body diode is formed by the N substrate connected to the drain and the P drift region on the top surface of the device. In an N channel MOSFET, the Anode of this diode is tied to the Source terminal of the device. The Cathode of this diode is then tied to the substrate. This diode gives us the freewheeling capability that BJT’s cannot. But it can come with its own problems. The majority of which revolve around reverse recovery. In the vast majority of double ended converters, those which use both positive and negative portions of the BH curve of the transformer to make output power, there is enough inductance in circuit to turn on the body diode of the opposite switch during any deadtime that may exist. The next event is to turn on the channel of the device. For the diode, this is problematic. The diode needs to sweep the minority carriers out of the junction to turn off. This action requires a certain amount of charge removal. If the Vf of the diode is suddenly clamped to 0V or so by the MOSFET channel, it takes a lot longer to pull that charge out than if the diode were to see a large blocking voltage. Most circuits tolerate this well, but at higher voltages where the intrinsic body diodes are a little tougher to switch off, it needs consideration at design. A lot of low voltage DC to DC converters with smaller duty cycles will place a Schottky in parallel with the lowside MOSFET to keep the body diode from turning on at all. This often improves the losses dramatically and allows for much smaller deadtimes.
Parasitic NPN turn on
The parasitic NPN transistor is formed by the N substrate (parasitic Collector), the P drift region (the Base) and the N well on the topside (the Emitter). More often than not this is totally benign, never seen in application. The reason for this is the very low impedance metallization that forms the source terminal covering both the Base and Emitter regions thereby maintaining the parasitic NPN in its off condition. Under extremely high speed voltage increase across the Vds terminals, the Crss of the device can couple enough current into the base of the parasitic NPN to turn it on. While this is not a latched condition, it is often catastrophic. At this point, the NPN is on, and thereby the MOSFET is conducting regardless of gate command.
Common source inductance
To understand common source inductance we need to take a look at the insides of a MOSFET. The die is attached to the Drain terminal via Epoxy, solder, or similar attach methodology. The drain terminal is a large metal terminal, often connected to the tab and substantial piece of the leadframe of the device. The source on the other hand is on the topside of the device. In a conventional package, the source is connected to the pin via bondwires. These bondwires have a small amount of inductance as does the lead pin.
The important interaction to remember is that both the drain current and the gate drive current have to exit the device through this source inductance, thereby giving rise to the term Common Source Inductance, often acronymed CSI. The problem with CSI occurs at high switching frequencies and high currents. If we look at the contributions, the drain current may cause 20 to 50A of current flow in the source inductance. The gate drive command may cause 1 or 2A of current. If we accept that 1 inch of wire in free air has 15 to 20nH of inductance, the bondwires and lead may contribute 5 to 10nH of inductance. That doesn’t sound like much, but if we consider how that inductance interacts with the gate drive command it is substantial. If we consider V=-Ldi/dt, we can see that the decaying slope of current through this inductance (albeit fast) actually adds voltage to the gate drive command. While the driver may command Vgs=0, the common source inductance may add several volts to this command thereby opposing the off command and keeping the device on.
Lead bending on most any device is more tricky than it looks, but in Hirel devices it is of highest concern. Normally the leads need to be clamped near the package when bent. This clamping effort keeps the leads from stressing the surrounding package material. In a plastic device, there’s often no hermiticity deliverable. In the hermetic HiRel devices, bending the leads has to use utmost caution. If the porcelain fillets around the lead are cracked, hermeticity is lost and contaminants will ingress.
We’ve discussed a plethora of problems that can arise thus far. Some simply can’t be seen. There is no way to see internal NPN turn on looking at the MOSFET terminals. We can’t see the voltage across the common source inductance because the other end of the measurement is inside of the package. There’s no waveform that will illustrate a bad bend and contaminant ingress other than the end waveform showing the failure. We can however measure Cdv/dt turn on events, Body diode reverse recovery, and various parasitic oscillations. To do this, the probe needs to have absolutely minimal loop area. There are several probe tip adaptors (sockets) available for this sort of work.
High Reliability MOSFETS are indeed pretty straightforward in use and application. They are very well characterized and tested. To keep the circuits running at optimal performance, there’s a few things that need to be understood. For example, when selecting a MOSFET for a static switch, with perhaps a slow turn on to charge a lot of capacitance on the equipment side from the DC bus, it is important to take a close look at the SOA and make certain that the device is operating inside of the DC portion of the curve. If selecting devices for a buck converter or a half bridge application there are many other considerations that dominate including total gate charge, Crss, and body diode performance. The next work on this subject will delve into various rad hard interactions and explanations.