FPGA and processor combinations deliver flexibility, computing power and savings to advanced embedded systems

Embedded systems designers, more than ever, are seeking flexibility in how they work with processing elements to help keep risks low, speed time to market and control cost. Traditional embedded systems often rely on general-purpose processors and microcontrollers or multicore processors. Once a processor is selected, the designer chooses the interface that corresponds with the specific processor. But many control and monitoring applications, for example, are demanding more complex solutions to reach their critical performance requirements.

To gain that flexibility, embedded systems designers are turning to heterogeneous processing. Heterogeneous computing simply means using multiple processors and different architectures to complete the computational task. Custom ASICs are one approach, but they can be costly to develop for specialized applications that aren’t tied to high volumes. Another approach is to harnesses an FPGA, which can be configured at run time and is reconfigurable during operation. Since FPGAs provide dedicated logic, the designer can use just one logic device for inline signal processing or other parallel tasks with more traditional processing elements to benefit from more cores and access to peripherals that may not be possible through other processors-based components, which in turn leads to higher performance and overall flexibility.

Lower-volume apps still demand computational power
So what are some of the complex applications suited for reconfigurable heterogeneous architectures? High-volume applications such as consumer electronics enjoy the economies of scale necessary to fabricate the expensive 28-nm and 22 nm chips being used today; their expense also means less variety for the lower-volume and specialized applications that still need the processing power.

Reconfigurable heterogeneous architectures (RHAs) consisting of a microprocessor and FPGA are increasingly used in advanced applications such as machine control, embedded control and monitoring, aeronautics, machine vision and inspection, and medical imaging. Control and monitoring applications, for instance, incorporate many sensors, actuators and application-specific buses and networks, each needing their own I/O. Flexibility and reconfigurability are thus achieved by connecting these disparate subsystems to an FPGA. Robust architecture environments, such as National Instruments’ reconfigurable I/O RIO hardware are suited to accommodate embedded systems in control and monitoring applications. The LabVIEW RIO architecture, for instance, routes all the specialized I/O through the FPGA to let the designer perform DSP on any or all I/O channels. IP can be optimized, so an engineer can create custom control architectures and even completely contain the entire control loop in the FPGA. They can also take advantage of the FPGA’s parallel characteristics to scale their systems to the desired channel count.

The parallel processing nature of FPGAs is also desirable in machine vision and inspection applications. Additionally, medical imaging are perfect for RHAs, where images can be broken up into parallel datapaths. One promising technology in medical diagnostics, optical coherence tomography (OCT), is similar to ultrasound, but measures light instead of sound and offers ultra-high-resolution capability. A collimated beam, reflected from the sample, can be detected and used to create an image. OCT technology is presented – in some circumstances – with a challenge known as “motion artifacts”, that can come from a body part not at rest or an internal tissue which cannot be fixed in place. An FPGA-based solution can provide the large number of DSP slices necessary to handle signal processing, Fourier transform processing and 3D imaging processing in an OCT application.

Increasingly, heterogeneous computing architectures are used in power electronics. Power converters, such as those with advanced batteries for grid-tied storage, benefit from FPGA-based architectures that include the processor. “In order to get the computing bandwidth and the high-speed I/O required to control, say, a solar inverter, FPGAs and these RHAs are playing a much larger role,” says Matt Spexarth, senior product manager for Embedded Systems at National Instruments. “That’s largely been a DSP-dominated world.” FPGA-based general purpose inverter controllers and their associated development platforms can alleviate low-level programming and full custom design concerns and liability while keeping costs and time-to-market in line.

Single-chip solutions save power and lower costs
While engineers can add FPGAs to their board-level design to create a custom solution, several vendors offer FPGA-based, single chip devices. The integration of multiple devices onto a single chip helps reduce system power, cost and board size. For instance, Cypress Semiconductor’s PSoC Programmable System on Chip includes a standard microprocessor architecture, a programmable logic array, high performance and programmable analog blocks, a programmable routing and interconnect and agraphical integrated design environment. Other examples include Xilinx’ Zynq-7000 All Programmable SoCs and Intel’s E600C processor which includes an Altera FPGA to provide designers with programmable logic.

Altera Cyclone V and Arria SoCs integrate an ARM Cortex A9 dual-core processor and peripherals with the FPGA fabric and are based on a low-power 28-nm process. In addition to their high integration, “The devices require no power-off sequencing, thus eliminating the need for external circuitry, says Steve Nirmal Kari, SoC product marketing manager at Altera. “These SoCs provide “enhanced system reliability with built-in ECC and memory protection that protect systems against potential hardware or software errors.” They feature a high-bandwidth interconnect between the processor and the FPGA for exceptional system performance, and engineers are able to customize both hardware and software, ensuring flexibility.

Hardened peripherals integrated into FPGA-based SoCs help control the configuration of the FPGA. “This significantly simplifies the process of reconfiguring the device from a variety of communication ports while retaining the security capabilities required during remote configuration,” according to Tim Morin, director product line marketing, new products, at Microsemi’s, SoC Products Group, whose SmartFusion2 SoC FPGAs are touted as true Flash-based FPGA. He notes, “The Flash configuration memory is stored within the FPGA fabric, so turn-on is similar to an ASIC.”

Prototype and simulate early
Design teams choose RHAs for the flexibility it allows them, plus the cost and time-to-market goals they can achieve using this approach. Equally important and perhaps overlooked is prototyping. Not only will the team have a proven design in hand, it will also be able to test the waters and determine if there’s a market for that product. This is especially important for start-ups that need to generate interest and funding in order to take that product to market.
Another important step, simulation, should take place before compilation. “Compiling logic for an FPGA takes orders of magnitude longer to convert from an algorithm to the bit stream compared to processor-based systems,” says NI’s Matt Spexarth. “Simulation before compilation makes it possible for you to test functionality of code in a real-time or trial-and-error way.” The company’s LabVIEW reconfigurable I/O (RIO) architecture offers tools and templates for designers including many software architectures and design patterns to get design teams going in the right direction. Likewise, chip vendors also provide robust ecosystems of development tools and support. “In any embedded system development project, software design typically takes up the bulk of time and resources,” says Nirmal Kari of Altera, whose SoC Embedded Design Suite (EDS) features utility programs, run-time software and application examples. “Developers get all the tools they need to work more productively, improve software quality and ultimately get to market faster.”

Matt Spexarth also suggests designers make sure they are getting all they can from their reconfigurable compute core. This can mean moving the FPGA from a peripheral support role to a more prominent role while providing the most flexibility and customization options. Jim Davis, Senior Product Marketing Manager for PSoC Platform at Cypress Semiconductor stresses designers eschew the paradigm of selecting a specific device to solve a specific problem. “Go back to the traditional design methods of drawing out a system block diagram and then identify what system functions can be implemented – regardless of how disparate the functionality – into a single RHA component.” He adds, “with RHA components, engineers now have the ability to time-multiplex the functionality the RHA component implements.” Reconfiguring a programmable block to perform a single function during a specific time slice of configuration and then returning it to its normal configuration using single-chip solutions such as Cypress’ PSoC is known as “dynamic” reconfiguration.

Finally, don’t overlook security. Tim Morin of Microsemi points out that RHA devices connected to the internet are vulnerable to malicious attacks, tampering and can even be vulnerable to a complete system takeover. The company’s SmartFusion2 SoC FPGAs tout desirable security capabilities and cryptographic services. “The IP within the design must be secured as well as the data (configuration bitstream, MCU boot code, applications code and sensitive application data) used by the design,” he adds.

As design teams weigh system performance demands, with cost and development times, ultimately sales, flexibility and risk are driving the decision to adopt FPGA-based reconfigurable heterogeneous architectures for complex applications. Advancements in single-chip RHA devices along with innovative development tools and ecosystems offer a wide breadth of design possibilities to help them attain their goals faster and smarter.