The OpenVPX effort, begun in early in 2009, culminated in ratification of ANSI/VITA 65 in mid 2010. This standard was the first to provide a system-level framework for VPX interoperability. Today, VPX modules are commonly used in very demanding, high bandwidth multi-processor signal processing applications, such as those used in military and aerospace C4ISR programs. To understand how the VITA 65 OpenVPX standard helps to promote interoperability among COTS products it is useful to review the module profiles and the appropriate backplane topologies and fabric types that are typically used by COTS signal processing modules. In addition, an understanding of the compatible COTS backplanes that speed development efforts for signal processing applications will aid system designers of these rugged signal processing applications to mitigate design risk and speed time to market.

The VPX problem for chassis & backplanes
The flexibility of the VPX board architecture (VITA 46), although a strength of the high-speed replacement for the venerable VME bus, also led to tremendous variation between different VPX module signal types and proprietary pin-outs. As a result, it became apparent, as system designers began to implement new system designs in the early days of the adoption of VPX, that a high percentage of these new VPX applications required custom backplane connectivity for interoperability between specific modules. Figure 1 shows the types of incompatible pinouts that were prevalent with early VPX modules. In addition, it was also found that for early VPX modules, power and cooling requirements varied widely.

To address these interoperability issues, the VITA 65/OpenVPX working group was formed. Part of its mission was to create a framework for interoperability. The resulting ANSI/VITA 65 OpenVPX framework consists of:
• Module Profiles
• Slot Profiles
• Backplane Profiles
• Development Chassis Profiles
• 5V-centric and 12V-centric Power Profiles

The ANSI/VITA 65 OpenVPX Profile Framework enables integrators to match up OpenVPX modules with compatible backplanes and chassis. The framework defines requirements for standard OpenVPX development chassis, which also helps to address significant issues related to power and cooling for OpenVPX systems.

Under the framework, compliant OpenVPX Air Cooled Development Chassis are designed to provide an air flow rate of 18 cfm/slot at 0.24” H2O and 5000 ft. This is a very high flow rate and pressure drop; most pre-existing development chassis cannot provide this much cooling. Compliant OpenVPX Air Cooled Development Chassis are designed to handle power and cooling for most available VPX modules.

To meet the needs of more demanding, harsher environments, the framework also defines compliant OpenVPX Conduction Cooled Development Chassis. These chassis are designed to maintain 55°C chassis rail temperature at 150 W/slot (6U) and 75 W/slot (3U) with 30°C ambient. Likewise, these conduction-cooled development chassis are designed to handle power and cooling for most available VPX modules.

Defining power
The ANSI/VITA 65 OpenVPX Profile Framework also addresses power supplies to ensure interoperability. Both 5V-centric and 12V-centric Power Profiles are defined for OpenVPX modules and Development Chassis, with >200W/slot for 6U and >100W/slot for 3U. In comparison, most pre-existing development chassis could not provide this much power.  

Standard COTS backplanes
There are today, available from a range of COTS suppliers, a selection of COTS backplanes that are compliant to standard OpenVPX Backplane Profiles. These backplanes include both Central and Distributed topologies. Previously, before the advent of ANSI/VITA 65, COTS interoperability for VPX systems was only possible for the simplest backplane architectures. Now that ANSI/VITA 65 OpenVPX has developed a defined framework, interoperability is much easier to achieve.

With a wide selection of COTS OpenVPX modules and backplanes offered from multiple vendors, such as Curtiss-Wright Controls Defense Solutions’ Electronics Packaging group, it is much easier for an integrator to configure an interoperable system by matching up the module profiles with compatible backplanes. The availability of ANSI/VITA 65 OpenVPX Development Chassis can significantly speed system development activities.

Module Profiles used by COTS signal-processing modules
COTS signal processing modules tend to use module profiles that support multiple fabric planes. For 3U form factors newer signal processing payload modules tend to use the MOD3-PAY-1F2F2U-16.2.2-x and MOD3-PAY-2F2U-16.2.3-x, and MOD3-PAY-1F1F2U-16.2.4-n module profiles. The fabric protocols used with these modules for the data plane is most commonly Serial RapidIO (SRIO) and PCI Express (PCIe).

The profile used for 6U system modules in newer signal processing payload modules tends to be MOD6-PAY-4F1Q2U2T-12.2.1-x and SRIO is the most commonly used fabric protocol for the data plane in these systems.

Backplane topologies and fabric types for signal processing applications
COTS signal processing systems tend to use backplane profiles that support multiple fabric planes. For 3U architectures, newer signal processing payload modules tend to use module profiles such as MOD3-PAY1F2F2U-16.2.2-x and MOD3-PAY-2F2U-16.2.3-x, and MOD3-PAY-1F1F2U-16.2.4-n. SRIO & PCIe are the most commonly used fabric protocols for the data plane. These module profiles are compatible with Backplane Profiles such as BKP3-CEN06-15.2.2-n, BKP3-CEN10-15.2.4 and BKP3-CEN12-15.2.6-n.

For larger 6U systems, newer signal processing payload modules tend to use module profiles such as MOD6-PAY-4F1Q2U2T-12.2.1-x, and SRIO is the most commonly used fabric protocol for the data plane. These module profiles are compatible with Backplane Profiles such as BKP6-CEN16-11.2.2-n, BKP6-CEN10-11.2.4-n, BKP6-CEN10-11.2.6-n, and BKP6-CEN05-11.2.5-n.

Standard OpenVPX Backplane Profiles for signal processing applications tend to have in common the use of one or more switch slots, separate data plane and control plane fabrics, as well as, in most cases, expansion plane fabric connectivity.

The data plane is a key for signal processing applications, which typically require very high bandwidth data transfer. The idea behind the additional planes is to offload the data plane to enable maximum performance.

The expansion plane provides local slot-slot data transfer, offloading this from the data plane; in signal processing applications this could be local connectivity from data converters or signal processing front end modules (e.g. FPGAs). It could also be used for local connectivity to a storage or recorder module.

The control plane provides an easily accessible Ethernet communication mechanism that can be used out of band, allowing full bandwidth communication on the data plane.

Compatible COTS backplanes to speed development of signal processing applications
VPX backplane suppliers now offer compliant COTS 3U and 6U OpenVPX backplanes for Gen1 as well as Gen2 fabric baud rates (up to 6.25 Gbaud standard). The availability of these backplanes enables system integrators to quickly configure an OpenVPX system from COTS chassis, backplanes, and modules

COTS OpenVPX modules, OpenVPX Development Chassis, and OpenVPX Backplanes are now available off-the-shelf, for both air cooled and conduction cooled development.  Several of these module and backplane profiles are specifically targeted at signal processing applications, including support for 6.25 Gbaud data plane and expansion plane fabrics; this supports Gen 2 fabric rates, providing increased performance. COTS Deployable OpenVPX chassis are also available, leveraging the standard OpenVPX backplanes. Availability of these OpenVPX compliant COTS products provides an interoperable ecosystem that system integrators can leverage for rapid prototyping and deployment.