Stephen J SwiftReducing the size of electronic products has become an increasingly important system design objective, especially in applications such as medical implantable devices that are used for a variety of new and emerging therapies and diagnostics. One of the most effective ways to shrink device size is to improve power efficiency so that devices need fewer and/or smaller batteries. In many cases, these batteries can represent up to a third or more of the total device footprint.

There are several ways improve power efficiency, including the use of duty cycling. This technique can dramatically improve efficiency by ensuring that major circuit sections only receive power when they are in use. Additionally, circuits should only be clocked when their function is required.

These and other techniques were used in a custom RF transceiver developed by Zarlink for the Pillcam wireless endoscopy imaging capsule from Given Imaging Ltd. The transceiver’s high level of power efficiency enables the Pillcam to relay up to 14 images per second during an eight-hour endoscopy procedure while consuming less than 7.5 milliwatts of power. The Pillcam only requires two small silver oxide batteries to provide the 3-volt supply for its journey through the digesivet tract (see Fig. 1). Future improvements in power efficiency and associated battery life will play a major role in enabling even smaller capsules with even more performance and functionality.

Figure 1: The Pillcam capsule’s high level of RF transceiver power efficiency enables it to operate on two silver dioxide batteries.

A second way to shrink implantable device size is to use space-efficient semiconductor packaging techniques, including chip-on-board assembly, chip-on-chip and, more recently, advanced 2-D and 3-D packaging. These techniqueshave had a very successfultrack record, reducing overall circuit space in cardiac rhythm management (CRM) devices by 60 percent to 80 percent. A stacked-die approach is particularly effective, because it decreases interconnect lengths and impedances, improvestesting, and allowsmultiple wafer process technologies to be combined in a small area.

Among the groups pursuingstacked-die advances is the Thin Interconnected Package Stacks (TIPS) project, which is funded by the IMEC R&D lab for nano-electronics in partnership with corporate and institutional entities including Zarlink. TIPS technology offers a number of important advantages as compared to earlier die-stacking approaches such as bare-die package-on-package (PoP), molded laser via PoP, molded laser via exposed die PoP, embedded die in laminate, Fan-Out Wafer Level Packaging (FO WLP) PoP, and silicon interposer/substrate. TIPS has proven more effective for reducing size (especially height), and also offers the advantage of a single module, which eliminates the yield loss associated with the PoP stacking process. Additionally, TIPS offers a more flexible package design, along with the potential for low cost at low volumes, with low tooling costs.

Device miniaturization will continue to grow in importance for a wide variety of applications. Power efficiency, in particular, is a major contributor to smaller devices, by enabling the use of smaller batteries that occupy less space. When power-efficient circuit design is combined with stacked-die packaging, there is even greater opportunity to significantly reduce the size of implantable medical devices and other electronic products.