Hector RiveraAs signal processing requirements continue to climb in waveform-intensive applications including unmanned aerial vehicles (UAV), sonar, radar, signals intelligence (SIGINT) and software defined radio (SDR), the use of multiple digital signal processors (DSP) cores is a key enabler. The multicore capabilities, combined with an expanding array of IP cores and development tools, enable sophisticated system architectures. All of these applications need multicore DSPs to meet the requirements of the mission critical industry, including more functionality (higher processing speed), finer resolution and increased accuracy. In the past, processor performance improvements have come through process node migration and higher operating clock frequencies. However, moving forward in small process technology nodes, increasing the clock frequency is not a power efficient way to increase performance. The approach of multiple cores in a single die provides the desired performance at lower clock rates and at lower power consumption.

Multicore DSPs are designed as system-on-chips (SoC) that include functionalities, such as network coprocessors, security accelerators or FFT accelerators. In order to meet performance requirements and cost targets for military applications, multicore DSPs should:

1. Support a mix execution engine (core),vector signal processing (VSP) and reduced instruction set computing (RISC);
2. Provide full multicore entitlement to enable all the capabilities available in the device;
3. Consist of a family of devices to enable scaling and reuse.

Today’s multicore devices consist of homogeneous cores, meaning all the processing cores are the same, or heterogeneous cores, meaning the device is a mix of core types. Nearly all applications require a mix of processing capabilities to meet industry requirements. From a developer perspective, it is important to support homogenous cores as heterogeneous system architectures can be created from homogeneous devices. The reverse is rarely true without degradation in performance. Figure one (below) highlights Texas Instruments’ KeyStone multicore architecture as an example of a heterogeneous multicore architecture. 

Figure 1. Texas Instrument’s KeyStone multicore architecture

The parallel processing capabilities provided by multicore DSPs provide a critical capability for demanding military applications. Radars demand faster FFT response time and depending on FFT requirements, developers can use all of the cores or some of the cores in the device for FFT implementation. If FFT performance can be met by using some of the cores, the other DSP cores can perform pre and/or post processing of the signals or other tasks in the system. Figure two highlights a parallel FFT example. There are standard software tools that provide multicore entitlement to determine the best core configuration (number of core) for the design in hand. These provide developers with the flexibility to meet multiple application requirements.

Figure 2-4. DSP parallelism FFT implementation

The state of multicore DSPs is evolving at a rapid pace. The newest multicore DSPs from semiconductor companies like Texas Instruments are based on a common architecture that helps developers reuse software and save development time for equipment manufacturers. Mutlicore DSPs are becoming lead differentiators for sonar, radar, SIGINT and SDR applications and are enabling the development of exciting new systems for today’s and tomorrow’s signal processing systems.