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Using light emitting diodes (LED) for automation equipment as indicator lights (lighted buttons and switches) often requires multiple modifications of the same control device depending on the available supply voltage. This approach severely complicates the logistics and affects the product cost. Moreover, some indicator light applications (elevator buttons, for example) require switching from the AC mains to a low-voltage backup battery supply for safety reasons. The engineers come back to this problem again and again, how to design a universal LED indicator lamp capable of operation in the wide range of input voltage from 24VDC to 265VAC. The conventional power supply topologies typically used for LED driver design, such as buck and flyback converters, are unable to satisfy these input conditions due to the excessive duty cycle range required. The goal of the present paper is to analyze a power topology which could be used as a universal LED indicator driver.

So-called “quadratic” converters [1] are known from the literature as power topologies featuring a wide range of the voltage conversion ratio m=Vo/Vg within a reasonable range of the duty cycle D=TON?fSW. (Here and below, Vo and Vg are the output and the input voltage correspondingly, TON is the on-time of the switch, and fSW is the switching frequency.) The example of such power topology is given in Fig.1, which depicts a 2-stage buck converter with peak-current control feedback.

In the conductive state of Q1, the path for the inductor L2 current is Q1-C1-D2-LED. Therefore, a positive voltage Vc-Vo develops across the inductor, and the current in L2 increases. At the same time, the current in the inductor L1 flows through the diode D2 in the opposite direction via the path C1-L1-DC-D2, and the current in L1 increases due to the positive voltage drop Vg-Vc. Of course, it’s been assumed that the current in L1 is less than the current in L2 in magnitude, which is true practically always, under a condition of continuous conduction of L1 and L2. During this state, the diodes D1 and D3 are reverse-biased and non-conductive.

In the non-conductive state of Q1, the path for the inductor L1 current is C1-D1, and the current in L2 flows through Co-D3, both currents decreasing. Thus, the cascade connection of the two buck stages is implemented, and the conversion ratio can be expressed as:

Such quadratic characteristic provides a wide range of voltage conversion ratio in the discussed power converter topology.

Note also, that the switch Q1 conducts the inductor L2 current only, and the peak current in Q1 does not depend on the current in L1. Hence, a simple peak-current control of the switch Q1 can achieve good regulation of the LED current.

It should be noted, that the input stage (D1, D2, L1, C1) is loaded by the current equal Io•D, and, correspondingly, the voltage across C1 equals Vo/D. Therefore, for continuous conduction mode (CCM) of L1, higher inductance value is required compared to the value of L2. Operating L1 in discontinuous conduction mode (DCM) for reducing its value is possible. However, this operating mode limits the dynamic range of the input voltage, and, therefore, it will not be analyzed within this paper.

The duty cycle D is dictated by the given range of Vg and Vo, and, in many cases, it exceeds 0.5. To avoid the subharmonic instability [2] under D>0.5, we will only consider a constant off-time switching mode of Q1. In this case, the inductances of L1 and L2 are given by the equations:

where k1 and k2 are the relative ripple coefficients k= ?I/I in the inductors L1 and L2.

Correspondingly, the inductors L1 and L2 should be designed for peak currents of

We neglected the current ripple in L1 in the equation (4) due to its small magnitude at Vg(min). The diodes D1 and D2 should be rated for the reverse voltage Vr=Vg(max). The reverse voltage at D3, generally speaking, equals the voltage at C1:

However, a certain margin is needed to account for the voltage spike due to charge redistribution between parasitic capacitances, when Q1 becomes conductive. The switch Q1 itself should be rated for the drain-source voltage of:

The value of the capacitor C1 will be discussed in the next section.

Stability of the circuit given in Fig.1 can be analyzed using a large signal average model shown in Fig.2. Since the peak current in L2 is unchanged in each individual switching cycle, in our model, we replaced L2 by a constant current source equal Io. Hence, the load of the input buck stage is modeled by a depending current source Io•D. On the other hand, the circuit in the lower part of Fig.2 reflects the mechanism of duty cycle modulation in accordance with the voltage transfer function of the output buck stage:

where ?v is a small perturbation of the voltage at C1.

Analysis of the model given in Fig.2 for small signals produces the open-loop transfer function given by:

From (9), the DC voltage gain eguals 1. However, the transfer function includes a resonant double pole at the frequency and a right-half-plane zero (RHPZ) at the frequency . The equation (9), therefore, shows that stability of the quadratic converter cannot be achieved without damping of the input buck stage, since the pole and the resonanse zero in the transfer function result in a 270° phase lag.

To achieve stability, a parallel damping network (Rd, Cd) can be used. The corresponding large-signal model is given in Fig.3. Analysis of this model produces the open-loop transfer function in the form:

The equation (10) gives a regular zero, an RHP zero and three poles. The first zero and the first pole are almost coinciding near the frequency 1/(2?RdCd), cancelling each other. Therefore, the equation (10) can be simplified almost without any sacrifice to the following form:

where n=Cd/C1.

Good results could be achieved with the following simple estimate, assuming critical damping of the resonant pole. In this case, the damping coefficient is assumed to equal ½.

Let us also assume that . Under these assumptions, the unity-gain crossing (0dB) occurs approximately at the natural resonant frequency . Hence, a phase margin of 45° is achieved. The condition of can now be solved for the required value of C1.

To achieve the desired damping factor, the capacitance Cd must be selected much greater than C1, i.e. n>>1.

The value of the damping resistor Rd can be obtained from the equation (12).

The quadratic buck converter described above can be easily implemented using the LED driver IC HV9921 by Supertex Inc. [3]

The HV9921 is a switching peak-current regulator IC operating in the fixed off-time mode with TOFF=10µs. The IC is powered through the switching MOSFET drain terminal. This allows using the HV9921 as the switch Q1 without any additional external circuitry. The driver circuit shown in Fig.4 provides tight regulation of the LED current and operates over a wide range of DC input voltage from 24V to 400V, as well as AC line voltage up to 265V(rms).

Literature:

[1] Dragan Maksimovi? and Slobodan ?uk, “Switching Converters with Wide Conversion Range,” IEEE Transactions on Power Electronics, Vol.6, ?1, Jan.1991, pages 151-157;

[2] Supertex Inc, “Constant, Off-time, Buck-based, LED Drivers Using the HV9910B,” Application Note AN-H50, page 2;

[3] Supertex Inc, “3-Pin Switch-Mode LED Lamp Driver IC, HV9921,” Datasheet.

**Quadratic buck converter**So-called “quadratic” converters [1] are known from the literature as power topologies featuring a wide range of the voltage conversion ratio m=Vo/Vg within a reasonable range of the duty cycle D=TON?fSW. (Here and below, Vo and Vg are the output and the input voltage correspondingly, TON is the on-time of the switch, and fSW is the switching frequency.) The example of such power topology is given in Fig.1, which depicts a 2-stage buck converter with peak-current control feedback.

In the conductive state of Q1, the path for the inductor L2 current is Q1-C1-D2-LED. Therefore, a positive voltage Vc-Vo develops across the inductor, and the current in L2 increases. At the same time, the current in the inductor L1 flows through the diode D2 in the opposite direction via the path C1-L1-DC-D2, and the current in L1 increases due to the positive voltage drop Vg-Vc. Of course, it’s been assumed that the current in L1 is less than the current in L2 in magnitude, which is true practically always, under a condition of continuous conduction of L1 and L2. During this state, the diodes D1 and D3 are reverse-biased and non-conductive.

In the non-conductive state of Q1, the path for the inductor L1 current is C1-D1, and the current in L2 flows through Co-D3, both currents decreasing. Thus, the cascade connection of the two buck stages is implemented, and the conversion ratio can be expressed as:

Such quadratic characteristic provides a wide range of voltage conversion ratio in the discussed power converter topology.

Note also, that the switch Q1 conducts the inductor L2 current only, and the peak current in Q1 does not depend on the current in L1. Hence, a simple peak-current control of the switch Q1 can achieve good regulation of the LED current.

**Steady-state considerations**It should be noted, that the input stage (D1, D2, L1, C1) is loaded by the current equal Io•D, and, correspondingly, the voltage across C1 equals Vo/D. Therefore, for continuous conduction mode (CCM) of L1, higher inductance value is required compared to the value of L2. Operating L1 in discontinuous conduction mode (DCM) for reducing its value is possible. However, this operating mode limits the dynamic range of the input voltage, and, therefore, it will not be analyzed within this paper.

The duty cycle D is dictated by the given range of Vg and Vo, and, in many cases, it exceeds 0.5. To avoid the subharmonic instability [2] under D>0.5, we will only consider a constant off-time switching mode of Q1. In this case, the inductances of L1 and L2 are given by the equations:

where k1 and k2 are the relative ripple coefficients k= ?I/I in the inductors L1 and L2.

Correspondingly, the inductors L1 and L2 should be designed for peak currents of

We neglected the current ripple in L1 in the equation (4) due to its small magnitude at Vg(min). The diodes D1 and D2 should be rated for the reverse voltage Vr=Vg(max). The reverse voltage at D3, generally speaking, equals the voltage at C1:

However, a certain margin is needed to account for the voltage spike due to charge redistribution between parasitic capacitances, when Q1 becomes conductive. The switch Q1 itself should be rated for the drain-source voltage of:

The value of the capacitor C1 will be discussed in the next section.

**Stability considerations**Stability of the circuit given in Fig.1 can be analyzed using a large signal average model shown in Fig.2. Since the peak current in L2 is unchanged in each individual switching cycle, in our model, we replaced L2 by a constant current source equal Io. Hence, the load of the input buck stage is modeled by a depending current source Io•D. On the other hand, the circuit in the lower part of Fig.2 reflects the mechanism of duty cycle modulation in accordance with the voltage transfer function of the output buck stage:

where ?v is a small perturbation of the voltage at C1.

Analysis of the model given in Fig.2 for small signals produces the open-loop transfer function given by:

From (9), the DC voltage gain eguals 1. However, the transfer function includes a resonant double pole at the frequency and a right-half-plane zero (RHPZ) at the frequency . The equation (9), therefore, shows that stability of the quadratic converter cannot be achieved without damping of the input buck stage, since the pole and the resonanse zero in the transfer function result in a 270° phase lag.

To achieve stability, a parallel damping network (Rd, Cd) can be used. The corresponding large-signal model is given in Fig.3. Analysis of this model produces the open-loop transfer function in the form:

The equation (10) gives a regular zero, an RHP zero and three poles. The first zero and the first pole are almost coinciding near the frequency 1/(2?RdCd), cancelling each other. Therefore, the equation (10) can be simplified almost without any sacrifice to the following form:

where n=Cd/C1.

Good results could be achieved with the following simple estimate, assuming critical damping of the resonant pole. In this case, the damping coefficient is assumed to equal ½.

Let us also assume that . Under these assumptions, the unity-gain crossing (0dB) occurs approximately at the natural resonant frequency . Hence, a phase margin of 45° is achieved. The condition of can now be solved for the required value of C1.

To achieve the desired damping factor, the capacitance Cd must be selected much greater than C1, i.e. n>>1.

The value of the damping resistor Rd can be obtained from the equation (12).

**Practical implementation**The quadratic buck converter described above can be easily implemented using the LED driver IC HV9921 by Supertex Inc. [3]

The HV9921 is a switching peak-current regulator IC operating in the fixed off-time mode with TOFF=10µs. The IC is powered through the switching MOSFET drain terminal. This allows using the HV9921 as the switch Q1 without any additional external circuitry. The driver circuit shown in Fig.4 provides tight regulation of the LED current and operates over a wide range of DC input voltage from 24V to 400V, as well as AC line voltage up to 265V(rms).

Literature:

[1] Dragan Maksimovi? and Slobodan ?uk, “Switching Converters with Wide Conversion Range,” IEEE Transactions on Power Electronics, Vol.6, ?1, Jan.1991, pages 151-157;

[2] Supertex Inc, “Constant, Off-time, Buck-based, LED Drivers Using the HV9910B,” Application Note AN-H50, page 2;

[3] Supertex Inc, “3-Pin Switch-Mode LED Lamp Driver IC, HV9921,” Datasheet.

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