Ian LandSystems used in electronic warfare (EW) and radar applications are essential parts of the strategic environment for threats on the ground, at sea and in the air. Since threats require rapid and shifting tactical responses, the design flexibility provided by programmable logic is essential in military hardware. Modern radar systems process signals in the Gigahertz frequency range. Many modern types of radar are Active Electronically Scanned Array (AESA) systems that have various modes enabled by digital signal processing, including modes for searching, identification, tracking, targeting and surveillance. Additionally, electronic warfare systems, such as the receiver jammer depicted in Figure 1, will also need the flexibility of an FPGA for low latency response and waveform agility. The majority of radar systems, whether steered mechanically or electronically, now process signals digitally to improve system flexibility with multiple modes using software-driven waveforms. 

Figure 1. Diagram of a typical electronic warfare receiver-jammer system.

Many radar systems require longer range and the ability to detect low-observable targets. Floating-point FPGAs enable this higher-precision processing that improves system dynamic range, reduces signal loss and improves the signal to interference and noise ratio. Single precision floating point provides the equivalent of 32-bit fixed point precision and eliminates overflow and other error conditions. In the past, radar and EW developers were forced to convert floating point algorithms to fixed point before it could be run in an FPGA. This is a laborious and error-filled process. Additionally, it lowered the accuracy and precision of the system. Only the latest generation of 28nm FPGAs is capable of offering a true floating point methodology.

To implement floating point in a system, a silicon structure that supports full floating-point processing, floating-point capable tools and a complete library of efficient floating-point functions are required. The DSP blocks in Altera's 28-nm Stratix V and Arria V FPGAs are specifically designed to meet the requirements of next-generation radar and electronic warfare systems. These FPGAs contain a variable-precision DSP architecture that allows designers to specify the required precision for each part of the design. This results in more efficient utilization of logic and DSP resources, as well as reducing power consumption, while providing higher-precision DSP where needed.

In addition to device architecture, look for a company that provides a set of tools and IP that supports floating point operations in an FPGA. The design entry flow should support the floating point FPGAs and include an interface to the tools such as Mathworks Matlab and Simulink. Altera’s Advanced DSP Builder software tool and the associated Advanced Blockset -- an integrated library of elements within Simulink – for example, provide algorithm entry and generate RTL code which is then used within the Quartus II development suite.

Variable precision DSP blocks are designed for various types of DSP processing, including various types of filter and fast Fourier transform (FFT) processing. Two DSP blocks can perform an 18x18 complex multiplier as shown in Figure 2, which is very helpful for finite impulse response and infinite impulse response filters. Three DSP blocks can perform an 18x25 complex multiplier that is perfect for fast Fourier transforms. This allows the DSP resources to increase in proportion to the bit precision growth on the data side of the multiplier and use fixed precision 18-bit twiddle factors, also known as coefficients. The result is a highly efficient use of DSP resources that allows designers to trade precision for usage of DSP block resources and associated power consumption at each radix stage of the FFT. Using these modes, the variable precision DSP architecture is well suited to perform parallel frequency-domain processing of data from large antenna arrays. 

Figure 2. Low-precision mode with variable precision DSP.

The precision and accuracy required in modern radar and certain electronic warfare systems are enhanced dramatically with floating point processing capability. Variable precision DSP block architectures support high precision modes which enable distant detection of low radar cross section aircraft, suppression of surrounding clutter and detection of slow moving targets, known as ground moving target indicator functionality. In addition, 27x27, 36x36 and 54x54 multiplier sizes allow efficient implementation of single-precision, single-extended and double-precision floating point operation for many options of high precision operation. 

Figure 3. High-precision Mode supports Floating Point Operation in an FPGA

FPGAs that support floating-point functionality provide a superior solution for DSP in radar applications. FPGAs offer better size, weight and power (SWaP) characteristics as a function of performance than other competing digital or analog processing solutions. Floating point FPGAs reduce system latency while improving dynamic range and reducing losses. By combining highly optimized silicon features and patented library functions with a floating-point DSP methodology, radar systems developed with these FPGAs can achieve the new standard of performance required by modern military applications.