Dave MooreToday’s military electronics demand increased mobility and extended operational life. This enhanced product viability requires significant SWaP (size, weight, and power) reductions. Through advanced microelectronic packaging solutions available from Avnet Electronics Marketing and Endicott Interconnect Technologies, Inc.(EI), we are achieving as much as 27 times reduction in physical size for existing printed wiring board assemblies, with significant reductions in weight and power consumption. Primary reductions in power are due to reduced interconnect lengths and corresponding load. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. As combat operations continue, electronics original equipment manufacturers (EOEMs) are searching for new ways to achieve SWaP reductions. By integrating the following design techniques and technologies, advanced packaging solutions have been successfully implemented to reduce electronics volume in numerous applications including SiP, partial bill-of-material (BOM) functional islands, MEMS sensor packaging, obsolete memory module replacement and processor/memory functional islands.

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Component Footprint Reduction
After performing a thorough BOM review, active components are reduced to the smallest available footprint, preferably, but not necessarily to bare die in flip-chip format. Passive components are embedded into the substrate layers or reduced to the smallest package form factor.

Introduce HDI Substrate Technologies
These thin, dense core and coreless stack-ups with fine circuit and interconnect features, provide the dense wireability necessary for bare die escape and component interconnect. Advanced production processes allow these particle filled substrates to be fabricated with 25-micron lines and spaces along with 50-micron laser drilled microvias. This small circuitry capability enables significant printed circuit size reductions. These laminated technologies have been engineered to provide excellent reliability, thermal, and electrical performance.

Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows EI to create individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 Ohm to 50 K-Ohm with tolerances from 5 to 20 percent and areas as small as 0.2 mm2.

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I/O Miniaturization
Since connectors may contribute a large percentage to product volume and weight, connector shrink is often realized by moving from pinned to SMT components. SMT connectors are available on smaller contact pitch and also in lower profile formats. Additionally, conversion to BGA interconnect can result in product miniaturization.

Integrated Circuit Assembly Capabilities
Aggressive, yet robust, component spacing, dual-sided component placement, and innovative 3D package solutions including package-on-package and die-on-die, result in significant surface area reduction. Implementing bare die flip-chip attach technologies, as opposed to packaged or wirebonded die, can also impact surface area reduction.

As the leading developer of system-in-package technical solutions, EI combines multiple integrated circuits (ICs), assembly and test technologies into high-reliability modular IC packages. EI formed an exclusive distribution agreement with Avnet Electronics Marketing in February 2011, combining Avnet’s global FPGA/ASIC design capability and design chain services with EI’s substrate and packaging expertise to provide defense/aero OEMs with highly reliable SWaP reduction solutions early in the design phase -- shortening cycle times and bringing the most competitive products to market faster.