Peter_ZdebelMarnix_TackA report published by the American Council for an Energy Efficient Economy (ACEE) estimates the US economy could expand by greater than 70 percent through 2030 and still use 11 percent less electricity, thanks to efficiency gains made possible via semiconductor technology. Progression, in terms of ultra low-loss MOSFETs/IGBTs, smart-power ICs, and intelligent power modules is already taking place. In addition, more advanced semiconductor substrates and innovative packaging solutions are on the horizon. The following article looks at the various areas in which headway is being made.

Improving power transistor technologies
A bipolar structure is presently preferred for power transistors with voltages >1kV, while MOSFETs are better for <1kV, especially at frequencies above 100kHz. IGBTs are chosen for high-current applications above this. Though silicon-based transistors continue to improve, within the next ten years limitations in this material will mean alternatives need to be sought. Employment of wide-bandgap materials (GaN, SiC and diamond) will become more common in this timeframe. These possess better thermal properties and offer lower switching losses, plus a more attractive combination of low on-state resistance (RDS(ON)) and high breakdown voltage (VBD).

The major challenges confronting development here have been in minimizing internal losses as switching frequencies continue to rise, by reducing conduction losses due to RDS(ON), lowering internal capacitances and improving reverse-recovery performance. Increasing breakdown robustness, thanks to higher VBD and UIS (Unclamped Switching Behavior), has also proved of importance.

Previously low-voltage MOSFETs (<40V) development concentrated on minimizing die size to reduce unit cost, for a given RDS(ON). The most important Figure-Of-Merit (FOM) was therefore the specific RDS(ON) RDS(ON)spec) measured in m? x mm2. Since in low-voltage FETs, the channel resistance has a large effect on RDS(ON)spec, the main effort was in fitting as many FET channels as possible into the available area. Planar channels were superseded by vertical ‘trench-gate’ channels, and advanced lithography employed to shrink surface dimensions.

The crucial FOM now, defined by RDS(ON)xQg(d), cannot be met simply by reducing the Trench-FET pitch, since improvements in RDS(ON)/area are offset by increasing Qg/area. Development is instead switching to architectures such as Trench-FETs with an additional decoupled vertical field-plate shielding the gate from the drain, Trench-LDMOS combining the compactness and backside drain from Trench-MOS with the lower Qg(d) of LDMOS, and LDMOS with optimized metallization/packaging. GaN-based HEMT technologies are also being developed as they combine low switching losses with low internal resistance.

A drive for lower cost and higher efficiency is also being witnessed when it comes to medium-voltage MOSFETs (40-200V), Frequencies heading towards a few hundred kHz mean a significant reduction of Qg(d) is called for. Decoupled vertical field plates using split-gate architectures can achieve RDS(ON)spec values similar to conventional field-plated structures, but with reduced Qg(d).

In high-voltage (200-1000V) MOSFETs, the most important contributor to RDS(ON) is the resistance of the drift region. Planar-FETs are still dominant here, whereas the 1D silicon limit (RDS(ON) ~ BV) restricts drift resistance. SuperJunction (SJ) devices, featuring charge-balanced vertical P-N pillars in the drift region, allow to break through the 1D silicon limit, thus outperforming planar-devices. The vertical field is spread over the depth of the pillars, resembling a thick intrinsic Si layer - creating a high BV, while keeping RDS(ON) low. First-generation SJ-devices exhibit 300 percent improvements in RDS(ON) compared to planar-FETs. Implementation of advanced deep-trench technology will allow to reach a 500 percent improvement.

Wide-bandgap materials also permit significant breakthroughs to be realized in high-voltage applications. GaN and SiC critical breakdown fields are an order of magnitude greater than silicon, and devices released so far also benefit from improved thermal conductivity (~3 times better than silicon). While SiC is the preferred material for >1kV applications, GaN is best suited to <1kV. Technological obstacles still need to be overcome, however. These include growing thick GaN layers on silicon to achieve high-voltage ratings, making enhancement-mode transistors, and raising reliability. Initial high-voltage GaN HEMTs are expected on the market in the next few years.

Utilization of smart-power ICs
The advent of combined Bipolar/CMOS/DMOS (BCD) technology has allowed the analog, digital and power aspects of system designs to be integrated onto a single monolithic substrate. This has led to the emergence of smart-power ICs. Successive BCD processes have improved high-voltage isolation, digital feature size (delivering greater analog accuracy, logic speed, density, etc) and power-handling. Modern processes enable integration of digital processors, RAM/ROM memory, embedded memory, and power drivers. Figure 1 shows how multiple functions can be combined in an automotive power SoC. 

Figure 1 - Power, logic and analog functions integrated on a single chip using BCDMOS process.

As CMOS geometries continue to shrink, the need for great embedded intelligence will lead to integration of 16/32-bit processors, multi-Mbit ROM/RAM and non-volatile memory, and complex digital IP. Analog functionality is also increasing, with demands for higher accuracy sensing mechanisms, high bit-rate data conversion, various interfacing protocols, pre-drivers/control loops, and accurate voltage/current references on chip. Power-drivers for 100-200V and 5-10A are being introduced with ultra-low RDS(ON) along with dense, robust high-voltage isolation architectures utilizing deep-trench and Silicon-On-Insulator (SOI) technologies.

Complementing technologies that serve applications <100V, integrated 600V transistors for AC/DC inverters are proving to be another important market. Advanced submicron CMOS processes will facilitate integration of low-cost, low RDS(ON) drivers moving from conventional LDMOS devices to double and triple RESURF DMOS, SJ LDMOS, and LIGBT.

Enhanced packaging technologies
Trends currently characterizing power semiconductor packaging mainly focus on improved interconnection, including wafer-level technologies to reduce resistance/parasitic effects, and enhanced on-chip heat spreading. Thick wirebonds of copper, gold or aluminum, as well as ribbon/clip bonding, and power-optimized chip-scale packages are improving Ohmic connection efficiency between the die and external electrodes. Figure.2 shows how package technology is evolving. 

Figure.2 - Power package integration roadmap.

Power semiconductor modules
Early power modules combined multiple thyristors/rectifiers in a single package to achieve higher power ratings. Over the last three decades major breakthroughs have been made. Today’s modules combine power semiconductors with sense, drive, protection and control functions. They are categorized into Intelligent Power Modules (IPMs), typically 1kW-30kW devices comprising power transistors/rectifiers, pre-drivers and possibly a controller, or Power Integrated Modules (PIMs), covering 10kW-1MW power ratings by parallelizing several IGBT/rectifiers. Use of Direct-Bonded Copper (DBC) has improved electrical performance, while ceramic substrates (such as Al2O3 and AlN) can simultaneously increase cooling efficiency. Improvements in package-assembly technologies are also focusing on planar co-integration of several dice and passives as well as vertical stacking technologies to increase system integration. ‘Un-packaging’ technologies, where several populated substrates are mechanically integrated by dispensing with housings, terminals and base plates, is another interesting field of research.

Low-voltage (<100V) modules are also appearing, driven by demands for improved power efficiency and cost for point-of-load converters. There is a clear trend here for switching frequencies >1MHz to be used in order to reduce component size and bill-of-materials costs, and novel techniques are being investigated to counteract switching losses.

Power electronics has an increasingly important place in our day-to-day lives. Continued innovation is essential if our hunger for more sophisticated technology can be married with the improved energy management needed to ensure long-term environmental stability. The trends discussed in this article show that the industry is facing up to the challenges it has been set, and will be able to deliver on them.

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