Isolating power-wasting components for near zero standby consumption
The most effective way to mitigate the impact of man’s energy use is to reduce power consumption. The need to reduce active-mode power consumption is obvious. Not so obvious is the need to minimize power drain in standby mode — when products are essentially doing nothing.
The standby consumption of electricity by domestic equipment and power adapters is quite significant. Lawrence Berkeley National Lab estimates that the waste in electricity resulting from standby and no-load consumption costs U.S. households over $5 billion each year1. According to the International Energy Agency, 5 to 15% of household electricity consumption (depending on country) is wasted in standby mode, and the European Commission estimates that standby consumes approximately 50 TWh of electricity per year in the European Union2.
Many consumer product OEMs are now producing electronic equipment with ultra-low standby power consumption, but the real goal is to achieve as close to zero power drain as possible. To optimize designs and achieve zero no-load3, two new high-voltage MOSFET ICs from Power Integrations enable designers to isolate power-draining elements in their circuits.
Cutting out standby power
The opportunity to make such savings has a direct impact on national requirements for provisioning of power stations and has consequently become a key element in the specifications issued by regulatory authorities. As an example, for TV receivers many programs including ENERGY STAR and EU Eco-Label now mandate a maximum standby consumption of 1 watt. The European Commission, as part of its energy-saving programs, has issued the Energy Using Products (EuP) Directive Lot 6 applicable for standby and off-mode losses of EuPs. Lot 6 came into force in early 2009 with progressively tightening requirements. As of 2010, the standby power consumption of new products must be less than 1 watt. In 2011, these values will be lowered for adapters to 300 mW for adapters ? 51W output or 500 mW for adapters > 51W output4.
In 2008, when EuP Lot 6 was finalized, the targets set were considered to be near the levels achievable with the best available technology. However, developments in switch-mode power ICs have moved ahead, and standby consumption levels much lower than the mandated requirements are now possible. Managers in many brand-name consumer product companies are aware of this and are demanding power consumption characteristics significantly better than national standards. For example, several major OEMs producing TVs and monitors have set a de-facto standard of 100 mW maximum standby consumption and other OEM in the computing market have set a much lower specification of 30 mW maximum – all of which are significantly lower than the national requirements.
Designing switch-mode power supplies (SMPS) for ultra-low power
Modern SMPS controller ICs have reached a level of sophistication such that the ability to meet standby consumption standards is almost inherent in their design. The power supply designer can produce an acceptable design simply by following the application notes. But to achieve a standby power consumption of one-tenth of the standards or lower requires considerable attention to detail. Each element of the power supply must be optimized, saving a few mW with each adjustment. Figure 1 shows the areas to be optimized in a typical flyback SMPS design.
This 20 W power supply (DER-188) is capable of providing standby output power of 0.2 W at 0.3 W input power and has a very low no-load consumption of <100 mW at 230 VAC. But what if the aim is to go much lower in standby, to as close to zero as possible?
The first component that comes to mind is the input filter. This element is connected directly to the mains supply input constantly, so any current consumption here must be eliminated. Resistors R1 and R2 also stand out because they connect directly across the input in parallel with the X capacitor C1. If the power supply were unplugged, the mains voltage present at the moment of disconnection would remain as a DC charge across the capacitor, hence across the pins of the mains plug. Because of the potential electric shock hazard, safety agencies mandate that for capacitance values above 100 nF, the voltage must be discharged with a time constant of below 1 second. The purpose of resistors R1 and R2 is to discharge capacitor C1. Two resistors are usually connected in series to meet safety agency single-point failure testing.
The presence of these resistors is highly undesirable from a power budget standpoint because they present a continuous drain irrespective of whether or not the power supply is functioning. In the application shown, the resistors are not needed because the input filter is designed with a 100 nF capacitor C1. But there could be a significant benefit to increasing the capacitance: the choke L1 could be made correspondingly smaller, producing savings in size, weight, and cost. But with a capacitance of 1 µF, for example, the combined value of R1 and R2 would have to be a maximum of 1 M?. At 230 VAC input, the resistors would continuously dissipate 53 mW.
Eliminate current drain
To achieve a standby current near zero, a solution must be found to eliminate the continuous current drain through R1 and R2. Power Integrations’ new CAPZero ICs provide an elegant answer. Figure 2 shows CAPZero in a typical application.
Each CAPZero device contains an integrated loss of AC detector and back-to-back MOSFETs in an SO-8 package. When the AC input voltage is present, CAPZero remains in an OFF state, blocking current flow in the discharge path and eliminating power losses. When the AC is removed, CAPZero turns on, thereby switching in the resistors and allowing discharge of the input filter capacitance. CAPZero is self-powered from the AC line with a power consumption of less than 5 mW at 230 VAC.
CAPZero is produced in two voltage ranges (825 V and 1 kV) and eight current ratings (from 0.25 mA to 2.5 mA). In being connected directly across the mains, the ability of CAPZero to withstand voltage surges is critical. In most consumer applications, the 825 V version may be used in association with a Metal Oxide Varistor (MOV). The 1 kV version may be used together with an MOV for applications where a surge requirement of up to 3 kV exists.
Figure 3 illustrates the operation of CAPZero under extreme conditions (see Reference Design Report RDR-252). In this test, the AC input was connected loosely in a manner so as to generate arcing at the contacts. This test demonstrates that the CAPZero device does not stay “latched-off” due to the arcing event and that it properly detects loss of AC power and safely discharges the X capacitor once the AC is removed.
CAPZero effectively isolates resistors R1 and R2, giving the designer the freedom to optimize the values of C1 and L1 and other input filter components. Being able to increase the value of the X capacitance without the power loss penalty allows the reduction in value/elimination of the common mode/differential mode chokes. Not only will this save space and cost, but this also provides efficiency improvements.
Having eliminated the current drain at the mains input, attention can be given to eliminating the current drawn by other elements in the circuit that continuously draw power even during standby. In higher power applications, there may be several signal paths/channels between high voltage rails and power supply controllers of power factor correction (PFC) and DC/DC converters. Examples include feed-forward or feedback signal paths connected to boost controllers in PFC systems and feed-forward signal paths in two-switch-forward/LLC/half and full bridge converters. A second new product from PI, SENZero, eliminates unnecessary power losses by isolating these signal paths/channels when they are not needed. A typical SENZero application is shown in Figure 4.
In this application, the internal gate drive and protection circuitry provides gate drive signals to the internal 650 V MOSFETs in response to the voltage applied to the VCC pin. This simple configuration provides easy integration into existing systems by using the system VCC rail as an input to the SENZero. This VCC rail is turned off when the power supply goes into standby mode, turning off the MOSFETs of SENZero to significantly reduce power losses to <500 µW per channel.
By using innovative components such as CAPZero and SENZero, the power supply designer now has the means to dramatically reduce power consumption under no-load and standby conditions. With these designs, the production of mainstream power supplies that consume close to no power in standby becomes economically viable. The goal of the European Commission to reduce standby electricity consumption within the EU by almost 75% by 2020 could well be a walk in the park.
About the Author
Edward Ong is the product marketing manager for energy saving devices at Power Integrations (PI). Prior to joining PI, Edward held the positions of program manager and product marketing manager at Emerson Network Power and R&D manager at ROHM Corporation. He holds an M.B.A. from Ateneo De Manila University, M.S.E.E. from De La Salle University, and B.S.E.E. from the Mapua Institute of Technology.
1. Reducing Leaking Electricity to 1 Watt, Meier, Huber & Rosen, Lawrence Berkeley National Laboratory, Berkeley, California. http://standby.lbl.gov/pdf/42108.html
2. Ecodesign: Commission reduces standby electricity consumption. European Commission. http://europa.eu/rapid/pressReleasesAction.do?reference=IP/08/2004
3. IEC 16301 clause 4.5 rounds standby power use below 5 mW to zero.
4. Commission Regulation (EC) No 278/2009 6 April 2009. The Commission of the European Communities. http://eur-lex.europa.eu/en/index.htm