Next-generation FPGA-based processing platforms for radar and electronic warfare (EW) systems provide a substantial increase in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover, unlike today’s digital signal processors, an FPGA can support a DSP datapath with mixed floating- and fixed-point operations, and achieve performance of 1000 GFLOPS. This is an important advantage, for many high-performance DSP applications that only require the dynamic-range provided by floating-point arithmetic in a subset of the total signal processing. The choice of FPGA implementation coupled with floating-point tools and IP allows the designer flexibility in a mix of fixed-point data width, floating-point data precision, and performance levels unattainable by a processor-based architecture. 

Figure 1. A Typical Block Diagram of a Radar System

These complex systems in military applications such as radar and EW are first simulated or modeled using floating-point data processing, using C or MATLAB software. However, final implementation is nearly always performed using fixed-point or integer arithmetic. The algorithms are carefully mapped into a limited dynamic range, and scaled through each function in the datapath. This requires numerous rounding and saturation steps, and if done improperly, can adversely affect the algorithm performance. This usually requires extensive verification during integration to ensure system operation matches simulation results and has not been unduly compromised. The use of floating-point arithmetic often provides enhanced performance due to large dynamic range and greatly simplifies the task of system performance verification against a floating-point simulation.

Newly developed FPGA tool suites have made floating-point arithmetic an attractive option for the FPGA designer. The key to efficient FPGA implementation of complex floating-point functions is to use multiplier-based algorithms, which leverages the large numbers of hardened multiplier resources integrated into FPGA devices. The multipliers used to implement these often non-linear functions, such as trigonometric operators, must have extra precision in the multipliers to keep the required precision through the multiply iterations. Additionally, as the multipliers carry extra precision, the need for normalization and denormalization at every single multiply iteration is reduced, which can result in significantly reduced logic and routing. This not only reduces resource usage, but can result in much higher circuit Fmax.

Today’s FPGAs incorporate hardened digital signal processing (DSP) blocks capable of implementing efficient 27-bit x 27-bit multipliers that provide extra bits above the normal single-precision 24-bit mantissa requirement for single-precision floating-point arithmetic. These multipliers also can be cascaded to build larger multipliers for double-precision floating-point applications, such as 54-bit x 54-bit size.

These techniques of floating-point circuit optimization have been used to build floating point IP cores, for common algorithms such as FFT, matrix inversion, logarithm and other functions providing exceptional FPGA floating-point performance. Additionally, current floating point performance has been benchmarked at 7 GFLOPs per watt, and further updates on floating point tool optimizations coupled with 28nm architecture of Stratix V FPGAs are expected to provide new benchmarks well in excess of 10 GFLOPs per watt.

Additional FPGA advantages are distributed internal memory, high external memory bandwidth and 12.5 Gbps SERDES transceiver performance. This FPGA platform also provides the highest performance fixed-point datapaths, which yield ultimate flexibility in I/O interfaces. With these capabilities, FPGAs offer an ideal platform to build high-performance, fixed and floating-point datapaths that can be leveraged for use on radar and EW applications.