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Sean Eilert- NumonyxToday’s advanced applications are creating an insatiable appetite for memory - driving the demand for new memory technology capabilities. As the market for more compact, more powerful electronic systems grows, designers are under increasing pressure to find new ways to fit the volume of code and data needed onto these shrinking devices. Phase Change Memory (PCM) meets these growing density, bandwidth, and scalability needs.

Density - With the convergence of consumer, computer and communication electronic systems, an exponential growth of code, and even faster growth of data, is occurring in all electronic systems. To accom¬modate this growth, memory density ranges must not only meet current needs but must also demonstrate the ability to scale to larger densities as required over time.

Bandwidth - In high-level “convergent” electronic systems, performance is measured in terms of bandwidth, to speed up Internet connections, to reduce power consumption, to enhance mobile use.The memory system design must support the increasing require¬ments of bandwidth and reduced power consumption.

Subsystem architecture - A key challenge for embed¬ded systems designers, memory parameters such as density, performance, packaging and interfaces all play a significant role in system-level performance. With the variety of memory types available to the system designer, it is viable to partition the memory subsystem according to the specific needs of the higher-level system and application components. In some cases, caching is a reasonable approach to achieve an appropriate balance of per¬formance, power and cost.

Scalability - System designers continue to face significant challenges to design reliable embedded and storage systems based on flash memory. With each new generation, the capabilities of existing memory technologies degrade, requiring significant system-level changes to maintain reliability and performance. Both NOR and NAND flash rely on memory structures that become increasingly difficult to shrink at smaller lithographies. PCM, however, is based on a physical state change of a chalcogenide material, com¬monly referred to as GST. Chalcogenide films have already been proven to have stable characteristics to a 5nm node1. As the PCM memory cell shrinks, the volume of GST material involved in the state change shrinks resulting in reduced power consumption or higher write performance.

PCM in Embedded Systems
A common use of memory in an embedded system is for code storage. Systems requiring a relatively small amount of memory, less than approximately 2Gb, are architected such that code is executed directly from the NOR flash (XiP). This memory is often used as storage memory for an embedded file system. DRAM is often used in these types of systems as a scratchpad memory.

In these types of systems, PCM can be used as a code execution memory. With its bit-alterable feature, PCM is able to displace some or all of the DRAM required in the system. (See Figure 1)

In SnD memory systems, PCM can reduce the density require¬ments for DRAM while fulfilling the density requirement of the NAND flash. At the same time, the presence of PCM in this type of system simplifies and improves the performance of file systems stored in the PCM due to the bit-alterability and low latency features.

PCM in embedded systems


PCM in Wireless Systems
The low-read latencies and fast memory overwrite capabilities of PCM also make it an ideal non-volatile XiP solution that scales from low- to high-density wireless solutions. It is common to find nearly independent subsystems for baseband and application processing in wireless systems. At the highest level, these can be considered independent embedded systems. Generally speaking, both subsystems have the need for a resident execution memory and for storage of small data structures. In many cases, the applications subsystem is also expected to store and perform operations on larger multimedia content. (See Figure 2)

With read latencies that are slower but on the same order of magnitude as the latencies of DRAM, albeit on smaller page sizes, PCM serves as an outstanding code execution memory and read-mostly memory for all but the most frequently manipulated data structures. The bit-alterability of PCM eliminates the need for block erase, which reduces the DRAM requirements even further, resulting in a lower cost memory subsystem.

PCM in Wireless Systems

PCM in solid state storage subsystems
PCM can be used in SSD systems to store frequently accessed pages and to store those elements which are more easily managed when manipulated in place. Examples of these types of elements include: parity bits for data stored in NAND, bad block tables, and block and page mapping tables. In this scenario, a small amount of PCM could be used to enhance the manageability of NAND. (See Figure 3) By minimizing the stress on the NAND memory, higher density MLC NAND is enabled, thus leveraging the capabil¬ity of PCM to lower the cost of the NAND flash in the subsystem. This caching with PCM will improve the performance and reliabil¬ity of the subsystem.

Additionally, when erased pages are scattered across many blocks (near full state), PCM can provide further reliability improvement. Managing a block-alterable memory in a near-full state implies that multiple erase cycles are likely required to free space to store the new data being written to the device. This increases the num¬ber of cycles on the device and further accelerates the time until the maximum endurance limits are reached. The bit-alterable nature of PCM solves the issue of increased write cycles when the device is full. Higher endurance of PCM addresses the needs of these systems when heavy use is expected.

Hybrid solid state storage

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