As applications engineers, we are constantly bombarded with a variety of questions about driving highspeed analogtodigital converters (ADCs) with differential inputs. Indeed, selecting the right ADC driver and configuration can be challenging. To make the design of robust ADC circuits somewhat easier, we’ve compiled a set of common “road hazards” and solutions. In this article, the circuit that actually drives the ADC—variously known as an ADC driver, differential amplifier, or diff amp—is assumed to be capable of handling highspeed signals.
Introduction
A basic fully differential voltagefeedback ADC driver is shown in Figure 1. Two differences from a traditional opamp feedback circuit can be seen. The differential ADC driver has an additional output terminal (V_{ON}) and an additional input terminal (V_{OCM}). These provide great flexibility when interfacing signals to ADCs that have differential inputs. Instead of a singleended output, the differential ADC driver produces a balanced differential output—with respect to V_{OCM}—between V_{OP} and V_{ON}. “P” indicates positive and “N” indicates negative. The V_{OCM} input controls the output commonmode voltage. As long as the inputs and outputs stay within their specified limits, the output commonmode voltage must equal the voltage applied to the V_{OCM} input. Negative feedback and high openloop gain cause the voltages at the amplifier input terminals, V_{A}+ and V_{A}–, to be essentially equal. For the discussions that follow, some definitions are in order. If the input signal is balanced, V_{IP} and V_{IN} are nominally equal in amplitude and opposite in phase with respect to a common reference voltage. When the input is singleended, one input is at a fixed voltage, and the other varies with respect to it. In either case, the input signal is defined as V_{IP} – V_{IN}. The differentialmode input voltage, V_{IN, dm}, and commonmode input voltage, V_{IN, cm}, are defined in Equation 1
This commonmode definition is intuitive when applied to balanced inputs, but it is also valid for singleended inputs. The output also has a differential mode and a common mode, defined in Equation 3 and Equation 4.
Note the difference between the actual output commonmode voltage, V_{OUT, cm}, and the V_{OCM} input terminal, which establishes the output commonmode level. The analysis of differential ADC drivers is considerably more complex than that of traditional op amps. To simplify the algebra, it is expedient to define two feedback factors, ß_{1} and ß_{2}, as given in Equation 5 and Equation 6.
In most ADC driving applications ß_{1} = ß_{2}, but the general closedloop equation for V_{OUT, dm}, in terms of V_{IP}, V_{IN}, V_{OCM}, ß_{1}, and ß_{2}, is useful to gain insight into how beta mismatch affects performance. The equation for V_{OUT, dm}, shown in Equation 7, includes the finite frequencydependent openloop voltage gain of the amplifier, A(s).
When ß_{1} ? ß_{2}, the differential output voltage depends on V_{OCM}—an undesirable outcome, since it produces an offset and excess noise in the differential output. The gainbandwidth product of the voltagefeedback architecture is constant. Interestingly, the gain in the gainbandwidth product is the reciprocal of the averages of the two feedback factors. When ß_{1} = ß_{2} ß, Equation 7 reduces to = Equation 8.
This is a more familiarlooking expression; the ideal closedloop gain becomes simply R_{F}/R_{G} when A(s) ® 8. The gainbandwidth product is also more familiarlooking, with the “noise gain” equal to 1/ß, just as with a traditional op amp. The ideal closedloop gain for a differential ADC driver with matched feedback factors is seen in Equation 9.
Output balance, an important performance metric for differential ADC drivers, has two components: amplitude balance and phase balance. Amplitude balance is a measure of how closely the two outputs are matched in amplitude; in an ideal amplifier they are exactly matched. Output phase balance is a measure of how close the phase difference between the two outputs is to 180°. Any imbalance in output amplitude or phase produces an undesirable commonmode component in the output. The output balance error (Equation 10) is the log ratio of the output commonmode voltage produced by a differential input signal to the output differentialmode voltage produced by the same input signal, expressed in dB.
An internal commonmode feedback loop forces V_{OUT, cm} to equal the voltage applied to the V_{OCM} input, producing excellent output balance. Terminating the Input to an ADC Driver The input resistance of the ADC driver, whether differential or singleended, must be greater than or equal to the desired termination resistance, so that a termination resistor, R_{T}, can be added in parallel with the amplifier input to achieve the required resistance. All ADC drivers in the examples considered here are designed to have balanced feedback ratios, as shown in Figure 2.
Because the voltage between the two amplifier inputs is driven to a null by negative feedback, they are virtually connected, and the differential input resistance, R_{IN}, is simply 2 × R_{G}. To match the transmissionline resistance, R_{L}, place resistor, R_{T}, as calculated in Equation 11, across the differential input. Figure 3 shows typical resistances R_{F} = R_{G} = 200 ?, desired R_{L, dm} = 100 ?, and R_{T} = 133 ?.
Terminating a singleended input requires significantly more effort. Figure 4 illustrates how an ADC driver operates with a singleended input and a differential output.
Although the input is singleended, V_{IN, dm} is equal to V_{IN}. Because resistors R_{F} and R_{G} are equal and balanced, the gain is unity, and the differential output, V_{OP} – V_{ON}, is equal to the input, that is, 4 V pp. V_{OUT, cm} is equal to V_{OCM} = 2.5 V and, from the lower feedback circuit, input voltages V_{A+} and V_{A–} are equal to V_{OP}/2. Using Equation 3 and Equation 4, V_{OP} = V_{OCM} + V_{IN}/2, an inphase swing of ±1 V about 2.5 V. V_{ON} = V_{OCM} – V_{IN}/2, an antiphaseswing of ±1 V about 2.5 V. Thus, V_{A+} and V_{A–} swing ±0.5 V about 1.25 V. The ac component of the current that must be supplied by V_{IN} is (2 V – 0.5 V)/500 ? = 3 mA, so the resistance to ground that must be matched, looking in from V_{IN}, is 667 ?. The general formula for determining this singleended input resistance when the feedback factors of each loop are matched is shown in Equation 12, where R_{IN, se} is the singleended input resistance.
This is a starting point for calculating the termination resistance. However, it is important to note that amplifier gain equations are based on the assumption of a zeroimpedance input source. A significant source impedance that must be matched in the presence of an imbalance caused by a singleended input inherently adds resistance only to the upper R_{G}. To retain the balance, this must be matched by adding resistance to the lower R_{G}, but this affects the gain. While it may be possible to determine a closedform solution to the problem of terminating a singleended signal, an iterative method is generally used. The need for it will become apparent in the following example. In Figure 5, a singleendedtodifferential gain of one, a 50 ? input termination, and feedback and gain resistors with values in the neighborhood of 200 ? are required to keep noise low. Equation 12 provides the singleended input resistance, 267 ?. Equation 13 indicates that the parallel resistance, R_{T}, should be 61.5 ? to bring the 267? input resistance down to 50 ?.
Figure 6 shows the circuit with source and termination resistances. The opencircuit voltage of the source, with its 50? source resistance, is 2 V pp. When the source is terminated in 50 ?, the input voltage is reduced to 1 V pp, which is also the differential output voltage of the unitygain driver.
This circuit may initially appear to be complete, but an unmatched resistance of 61.5 ? in parallel with 50 ? has been added to the upper R_{G} alone. This changes the gain and singleended input resistance, and mismatches the feedback factors. For small gains, the change in input resistance is small and will be neglected for the moment, but the feedback factors must still be matched. The simplest way to accomplish this is to add resistance to the lower R_{G}. Figure 7 shows a Thévenin equivalent circuit in which the above parallel combination acts as the source resistance.
With this substitution, a 27.6? resistor, R_{TS}, is added to the lower loop to match loop feedback factors, as seen in Figure 8.
Note that the Thévenin voltage of 1.1 V pp is larger than the properly terminated voltage of 1 V pp, while the gain resistors are each increased by 27.6 ?, decreasing the closedloop gain. These opposing effects tend to cancel for large resistors (>1 k?) and small gains (1 or 2), but do not entirely cancel for small resistors or higher gains. The circuit in Figure 8 is now easily analyzed, and the differential output voltage is calculated in Equation 14.
The differential output voltage is not quite at the desired level of 1 V pp, but a final independent gain adjustment is available by modifying the feedback resistance as shown in Equation 15.
Figure 9 shows the completed circuit, implemented with standard 1% resistor values.
Observations: Referring to Figure 9, the singleended input resistance of the driver, R_{IN, se}, has changed due to changes in R_{F} and R_{G}. The driver’s gain resistances are 200 ? in the upper loop and 200 ? + 28 ? = 228 ? in the lower loop. Calculation of R_{IN, se} with differing gain resistance values first requires two values of beta to be calculated, as shown in Equation 16 and Equation 17.
The input resistance, R_{IN, se}, is calculated as shown in Equation 18.
This differs little from the original calculated value of 267 ?, and does not have a significant effect on the calculation of R_{T}, since R_{IN, se} is in parallel with R_{T}. If a moreexact overall gain were necessary, higher precision or series trim resistors could be used. A single iteration of the method described here works well for closedloop gains of one or two. For higher gains, the value of R_{TS} gets closer to the value of R_{G}, and the difference between the value of R_{IN, se} calculated in Equation 18 and that calculated in Equation 12 becomes greater. Several iterations are required for these cases. This should not be arduous: Recently released differential amplifier calculator tools, ADIsimDiffAmp™ (Ref. 2) and ADI Diff Amp Calculator™(Ref. 3) downloadable, do all the heavy lifting; they will perform the above calculations in a matter of seconds. Input CommonMode Voltage Range
It may be useful to recall that V_{A} is always a scaleddown version of the input signal (as seen in Figure 4). The input commonmode voltage range differs among amplifier types. Analog Devices highspeed differential ADC drivers have two input stage configurations, centered and shifted. The centered ADC drivers have about 1 V of headroom from each supply rail (hence centered). The shifted input stages add two transistors to allow the inputs to swing closer to the –V_{S} rail. Figure 10 shows a simplified input schematic of a typical differential amplifier (Q2 and Q3).
The shifted input architecture allows the differential amplifier to process a bipolar input signal, even when the amplifier is powered from a single supply, making them well suited for singlesupply applications with inputs at or below ground. The additional PNP transistor (Q1 and Q4) at the input shifts the input to the differential pair up by one transistor V_{be}. For example, with –0.3 V applied at –IN, point A would be 0.7 V, allowing the differential pair to operate properly. Without the PNPs (centered input stage), –0.3 V at point A would reverse bias the NPN differential pair and halt normal operation. Table 1 provides a quick reference to many specifications of Analog Devices ADC drivers. A glance reveals the drivers that feature a shifted ICMVR and those that do not. Table 1. HighSpeed ADC Driver Specifications
Input and Output Coupling: AC or DC An accoupled input stage is illustrated in Figure 11.
For differentialtodifferential applications with accoupled inputs, the dc commonmode voltage appearing at the amplifier input terminals is equal to the dc output commonmode voltage, since dc feedback current is blocked by the input capacitors. Also the feedback factors at dc are matched and exactly equal to unity. V_{OCM}—and consequently the dc input commonmode—is very often set near midsupply. An ADC driver with centered input commonmode range works well in these types of applications, with the input commonmode voltage near the center of its specified range. ACcoupled singleendedtodifferential applications are similar to their differentialinput counterparts but have commonmode ripple—a scaleddown replica of the input signal—at the amplifier input terminals. An ADC driver with centered input commonmode range places the average input commonmode voltage near the middle of its specified range, providing plenty of margin for the ripple in most applications. When input coupling is optional, it is worth noting that ADC drivers with accoupled inputs dissipate less power than similar drivers with dccoupled inputs, since no dc commonmode current flows in either feedback loop. AC coupling the ADC driver outputs is useful when the ADC requires an input commonmode voltage that differs substantially from that available at the output of the driver. The drivers have maximum output swing when V_{OCM} is set near midsupply; this presents a problem when driving lowvoltage ADCs with very low input commonmode voltage requirements. A simple solution to this predicament (Figure 12) is to accouple the connection between the driver output and the ADC input, removing the ADC’s dc commonmode voltage from the driver output, and allowing a commonmode level suitable for the ADC to be applied on its side of the accoupling. For example, the driver could be running on a single 5V supply with V_{OCM} = 2.5 V, and the ADC could be running on a single 1.8V supply with a required input commonmode voltage of 0.9 V applied at the point labeled ADC CMV.
Drivers with shifted input commonmode ranges generally work best in dccoupled systems operating on single supplies. This is because the output commonmode voltage gets divided down through the feedback loops, and its variable components can get close to ground, which is the negative rail. With singleended inputs, the input commonmode voltage gets even closer to the negative rail due to the inputrelated ripple. Systems running on dual supplies, with singleended or differential inputs and ac or dccoupling, are usually fine with either type of input stage because of the increased headroom. Table 2 summarizes the most common ADC driver inputstage types used with various inputcoupling and powersupply combinations. However, these choices may not always be the best; each system should be analyzed on a casebycase basis. Table 2. Coupling and InputStage Options
Output Swing For applications where every last millivolt of output voltage is required, Table 1 shows that quite a few ADC drivers have railtorail outputs, with typical headroom ranging from a few millivolts to a few hundred millivolts, depending on the load.
Figure 13. Harmonic distortion vs. V_{OCM} at various frequencies for the ADA4932 with a 5V supply. Figure 13 shows a plot of harmonic distortion vs. VOCM at various frequencies for the ADA4932, which is specified with a typical output swing to within 1.2 V of each rail (headroom). The output swing is the sum of V_{OCM} and V_{PEAK} of the signal (1 V). Note that the distortion starts to take off above 2.8 V (3.8V_{PEAK}, or 1.2 V below the 5V rail). At the low end, distortion is still low at 2.2 V (–1 V_{PEAK}). The same type of behavior will appear in the discussions of bandwidth and slew rate. Noise All ADCs inherently have quantization noise, which depends on the number of bits, n, decreasing with increasing n. Because even “ideal” converters produce quantization noise, it will be used as a benchmark against which to compare random noise and harmonic distortion. The output noise from the ADC driver should be comparable to or lower than the ADC’s random noise and distortion. Beginning with a review of the characterization of ADC noise and distortion, we will then show how to weigh ADC driver noise against the ADC’s performance. Quantization noise occurs because the ADC quantizes analog signals having infinite resolution into a finite number of discrete levels. An nbit ADC has 2^{n} binary levels. The difference between one level and the next represents the finest difference that can be resolved; it is referred to as a least significant bit (LSB), or q, for quantum level. One quantum level is therefore 1/2^{n} of the converter’s range. If a varying voltage is converted by a perfect nbit ADC, then converted back to analog and subtracted from the ADC’s input, the difference will look like noise. It will have an rms value of (Equation 21):
From this, the logarithmic (dB) formula for the signaltoquantizingnoise ratio of an nbit ADC over its Nyquist bandwidth can be derived (Equation 22); it is the best achievable SNR for an nbit converter. Random noise in ADCs, a combination of thermal, shot, and flicker noise, is generally larger than the quantization noise. Harmonic distortion, resulting from nonlinearities in the ADC, produces unwanted signals in the output that are harmonically related to the input signals. Total harmonic distortion and noise (THD + N) is an important ADC performance metric that compares the electronic noise and harmonic distortion to an analog input that is close to the fullscale input range of the ADC. Electronic noise is integrated over a bandwidth that includes the frequency of the last harmonic to be considered. Here, the “total” in THD includes the first five harmonicdistortion components, which are rootsumsquared along with the noise (Equation 23).

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