Designing with CPLDs
By Gordon Hands, Lattice Semiconductor
Many designs require a small amount of high-speed, instant-on programmable logic. These designs drive the thriving market for Complex Programmable Logic Devices (CPLDs). This article examines the definition of CPLDs, their applications, design methodologies and which factors to consider when selecting a CPLD.
What Makes a CPLD a CPLD?
There are several characteristics that define a device as a CPLD rather than as a Field Programmable Gate Array (FPGA).
Most designers agree that a CPLD device must have embedded non-volatile memory to provide a single chip solution that boots quickly. In addition, pin-to-pin timing must be fast, in the 5nS or lower range. There are other criteria as well, but these are best understood by reviewing the different architectural approaches to CPLD implementation.
Traditionally, CPLDs have implemented logic by forming an OR function of many wide (high input) AND terms that are often referred to as Product Terms (PTs). Each OR typically is associated with a register, and the combination of a register, the OR gate and its associated PTs is commonly referred to as a macrocell. A typical example of this architecture is found in the Lattice ispMACH4000 CPLD. This particular architecture delivers fast logic and simple to analyze timing, a characteristic often referred to as deterministic.
Over the last few years, improved silicon processing technology and advanced design software tools have spawned a new class of LUT (Look Up Table)-based CPLDs. LUT-based devices have been able to deliver the speed and timing certainty that in the past have been associated only with PT- based architectures. In LUT-based devices, a 4-input LUT typically is combined with a register to form the basic unit of logic. This combination is often referred to as a LUT as well. A typical example of this architecture is found in the Lattice MachXO.
Typical CPLD Applications
CPLD devices are used for a myriad of functions in a vast variety of applications. These four are among the most common applications that are suited to CPLD devices:
Most systems have a small amount of logic that holds the various digital components in reset until a power good signal is received. After power has been declared good, then the logic brings these various devices out of reset in a controlled manner. For this application it is often critical that the reset logic be available very rapidly after power up. Failure to assert the appropriate reset signals quickly can lead to inappropriate system operation, accidental data corruption and device contention.
FPGA and ASIC/ASSP Provisioning
An expansion of the reset logic application is FPGA and ASIC/ASSP provisioning. In this application, it is necessary to configure certain devices prior to system start. Typically, data must be loaded from a Flash memory to an FPGA or certain registers in an ASIC or ASSP device. -
All newer CPLD families provide support for multiple I/O standards. This I/O flexibility, coupled with small size, high-speed and low-cost, makes CPLDs an ideal way to accommodate voltage among the different I/O interfaces used in a system.
It is often the case that an ASIC, microprocessor or FPGA does not provide the number of I/Os required for an application. By implementing a simple serial bus between a CPLD and another device, the CPLD can be used as a low cost way to provide additional, moderate performance I/Os
CPLD Design Approaches
The design approaches available for CPLDs vary, depending on the underlying architecture. For PT-based devices, designers can choose simpler input languages such as ABEL, or more complex languages such as VHDL or Verilog. Some designers prefer ABEL for PT-based designs due to either their past experience or its simplicity. However, Verilog and VHDL are becoming more popular, because they provide more flexibility to target other architectures and technologies. Independent of the specific language chosen, describing the logic in equation form is recommended in order to exploit the wide AND functions and have tight control over the timing. For designers using LUT-based architectures, VHDL or Verilog are used almost exclusively for new designs. Occasionally, schematic editors are used to provide a graphical view at the top level of a design.
Another difference in design approach that occurs as a result of the underlying technology is the importance of timing preferences and floor planning. With PT-based architectures, little floor planning is needed because the routing delays are approximately constant throughout the device. Limited timing preferences are needed, because the primary determinate of performance is the amount of logic in which the function is implemented. This can be controlled by constructing equations carefully when creating a design. With LUT-based devices, there are many more variables in routing delays and a wide variety of ways to place logic. In this situation the use of preferences and floor planning becomes significantly more important.
What Makes Sense For Your Design?
So, you are working on your next design and need a small amount of logic that powers up instantly, and you need to select the most appropriate part. A CPLD will do the job, but should it be a PT-based device, or a LUT-based device? Here are some questions to ask in order to decide.
How much logic do you need?
As a rule of thumb, one macrocell is equivalent to two LUTs or 25 ASIC gates. Currently there are no LUT-based CPLD solutions below 128 macrocells, or approximately 3000 ASIC gates. At the 128 macrocell / 256LUT level, pricing is approximately equivalent. Above 128 macrocells, the LUT-based approach is generally cheaper per unit of logic.
How wide are your functions?
Generally, PT-based devices are good for implementing very wide functions efficiently and at high speeds. For example, a 32-bit decode can be implemented in a single AND term. The LUT-based approach can be faster for narrow functions, but it has to build wide functions out of many levels of LUTs, leading to slower performance.
How important is deterministic timing?
Some applications require tight control over timing. For instance, a device used to provide interface standard conversion with no internal registering may require a very similar delay on each path. For these functions, the PT-based architecture makes these functions easy to implement. Alternatively, if the design is fully registered and you are familiar with using timing preferences, then a LUT-based device can be used.
What is the ratio of registers to logic in you design?
LUT-based architectures have about twice as many registers per gate as the PT-based alternatives. If the design makes extensive use of registers, then a lower cost of implementation will be achieved with a LUT-based architecture.
Beyond these general considerations, specific package, I/O standard, power consumption and other requirements need to be considered when selecting the CPLD architecture.