Christopher J. Loberg, TektronixFor years, synchronous parallel buses have served as the media for data exchange between digital devices. Timing issues, however, plague parallel buses at high clock frequencies and data rates, and limit their capability to keep up with demands of higher-speed computers. Over the past few years, serial-bus technology has advanced the computer industry because serial buses send self-clocking bit streams that eliminate skew associated with parallel buses. As a result, serial data rates have risen above 1 Gbits/sec. and newer implementations approach 3 to 6 Gbits/sec. As multi-gigabit data rates become common, however, signal integrity -- the quality of signal needed to properly transmit data to an IC -- becomes a paramount concern for designers.

Tests of serial-data designs have evolved in step with the increases in data rates. To assist engineers, organizations that oversee serial standards, such as PCI Express and Serial ATA, provide a set of recommended testing specifications. As data rates have exceeded 1 Gbits/sec., the standards have begun to emphasize receiver stress testing. Because tolerances for bit thresholds, measured in picoseconds and microvolts, have become ever more precise, the exposure of a circuit to noise, jitter, crosstalk, distributed reactances, power-supply variations, and other effects can greatly diminishes the quality of a received signal.

To stress test a serial receiver’s ability to determine bit values in a predictive fashion, engineers must reproduce the effects caused by the conditions noted earlier. As a result, engineers rely on analog waveforms than can accurately mimic imperfections in high-frequency serial bit streams. To create these signals, new test instruments rely on the direct digital synthesis (DDS) technique described first in 19711. This technique lets engineers duplicate the rise times, pulse shapes, delays, and aberrations that a signal would experience as it propagates through a transmission line. A test signal of this type provides just what engineers need for rigorous serial-bus testing.

Figure 1. A high-frequency arbitrary waveform generator (AWG) such as this Tektronix AWG7000 lets engineers edit test signals and alter them to stress high-frequency serial-digital data receivers.
Figure 1. A high-frequency arbitrary waveform generator (AWG) such as this Tektronix AWG7000 lets engineers edit test signals and alter them to stress high-frequency serial-digital data receivers.
Data Points the Way to Signal Imperfections

The DDS technique depends on a sample-based technology. Whereas an analog signal generator uses an oscillator to produce continuous waveforms, a DDS signal source, or arbitrary waveform generator (AWG), creates analog waveforms from discrete data points. Its output represents digital data typical of the signals you would see on a serial bus. The sample points in an AWG’s memory can define essentially any waveform, including digital pulses. Of course, the normal limitations of physics and bandwidth still apply, but within its specified frequency range, an AWG can produce a 5-Gbit/sec. serial data packet as easily as it can create a 440-Hz piano note.

Newer AWGs (see Figure 1) can create signals at the high data rates common in the latest serial buses. These instruments offer rates up to 20 GSamples/sec on several outputs and ample memory to create long bit-pattern sequences.
Different Approaches to Add Jitter Amplitude

As an example of the utility of a DDS-based AWG, consider the addition of jitter to a serial bit stream. Jitter, a signal-integrity phenomenon, slightly varies bit timing and tends to "smear" signal edges and makes itself evident as a narrowing of the "eye" opening in an oscilloscope's display of a signal. Traditionally, tests have used a pattern generator to stress test a receiver and a timing/pattern generator, or data generator, to add jitter to the bit stream.

Figure 2. This receiver stress-test diagram shows the many components and instruments -- all of which require careful calibration -- needed to perform traditional receiver and transceiver tests. (Click image to enlarge) 
Figure 2. This receiver stress-test diagram shows the many components and instruments -- all of which require careful calibration -- needed to perform traditional receiver and transceiver tests. (Click image to enlarge)

The following example contrasts the traditional data- and pattern-generator method with a method that uses the DDS technique. Figure 2 depicts a typical setup for jitter measurements on a receiver. The equipment can deliver data patterns that contain random and deterministic jitter.

This approach requires an engineer to add jitter to the transmitted signal until the receiver, or device under test (DUT), starts to detect frame or bit errors at a specified rate. The engineer then measures the jitter amplitude to determine whether the DUT meets its specifications. The test equipment in this example can produce any type of jitter the receiver might experience in actual use.

The receiver’s architecture complicates this test arrangement. A standard, such as that for Serial ATA, requires the receiver to follow built-in self test (BIST) instructions delivered within a specific frame information structure. Serial transceivers, those with transmitter, receiver, and serialize-deserialize (serdes) elements, go into a special loopback mode when they receive a sequence of BIST-loopback (BIST-L) frames. In this condition, the device echoes the signal it receives.

The diagram in Figure 2 shows the use of a power combiner that connects to a PC that creates the BIST-loopback commands and to a signal generator that provides the test data stream. In this configuration, the data generator can begin to transmit test data to the DUT as soon as the PC activates the loopback mode. But, the power combiner adds to the test system another component that can affect the test signals. It also requires that test engineers calibrate all of the input sources to ensure they introduce the expected jitter components. The power combiner can attenuate the data signal voltage by up to 50 percent. Although engineers can increase the data generator’s output amplitude, that action also increases noise and, potentially, distortion. All in all, the tests require a complex arrangement of equipment.

Figure 3. The WiMedia waveform display lets engineers use a graphical display to create test signals that include real-world defects such as noise and jitter. (Click image to enlarge, then maximize window to show details)
On the other hand, a DDS-based AWG can create the needed jitter amplitude and it can encode the BIST instruction set within the test signal. No need for an added PC. To create this type of signal, engineers must have tools that let them capture, edit, and validate the waveforms needed for stress testing.

Use the Right Tool for Your Protocol

To create test signals, many engineers use a modeling tool such as MATLAB from The Mathworks. But because engineers must work with standard protocols, they may feel more comfortable with tools that let them start with the graphical protocol format, which software then translates into a test bit stream. In addition, engineers can include jitter and change the test signal in other ways to stress receivers and transceivers. The image in Figure 3 displays a WiMedia view of the protocol layer suitable for waveform creation and editing within the Tektronix RF Express software.

The introduction of high-speed, high sample-rate AWGs gives engineers the capability to create precise and reproducible test signals, replay captured signals and add noise and jitter to signals. This class of AWG could also pre-emphasize and de-emphasize signals, and produce multi-level signals at rates as high as 10-Gbits/sec. In addition, engineers can download a library of waveforms created to test devices to specifications included in standards such as SATA, WiMedia, high-speed USB, and Ethernet.


1 Tierney, J., C. M. Rader and B. Gold, "A Digital Frequency Synthesizer," IEEE Transactions on Audio and Electroacoustics AU-19:1, March 1971.

Chris Loberg is the Worldwide Senior Manager of Marketing for Performance Instruments at Tektronix. He received an MBA degree in Marketing from San Jose State University and now resides with his family in Beaverton, OR. For more information, contact Tektronix, Inc., 14200 SW Karl Braun Drive, Box 500, Beaverton, OR 97077; (800) 835-9433;