Lower output voltages, higher current densities, increasing switching frequencies and smaller real estate are well-known trends in applications such as desktop PCs, servers, telecom point of load (POL) as well as other, similar DC/DC converter systems. Simultaneously, designers have strived to increase system efficiency, reduce total solution cost and simplify their designs. To this end, several design approaches implementing discrete components have been tried and tested. This article follows the evolution of this approach and describes the latest adoption of multi-chip modules for solving these design challenges.

Discrete Approach

In the computing space, particularly in desktop PCs and servers, a typical VR11.x design may use a four-phase DC/DC converter approach based on discrete components. Such a system typically uses three DPAK devices per phase, one as a high-side and two as low-side FETs.

Advances in MOSFET technologies and improvements in silicon processes have allowed designers to progressively optimize discrete-based buck converters. High-side FET devices have been continuously optimized for fast switching performance with lower gate charge and reduced gate resistance values. Through higher cell density silicon technologies, low-side FETs have achieves lower drain to source resistance. These improvements have been accompanied by reduced costs, a critical demand from computer manufacturers. However, the discrete approach presents several limitations:

• Limited system efficiency due to parasitic inductances in board layout paths connecting discrete components, and lead inductances in packages such as DPAK and SO8. This limitation is more noticeable at higher frequencies.
• Considerable use of real estate in PCB. In desktops and servers, the total power delivery components in a motherboard can occupy up to 30 percent of the board area.
• Longer design time and the inevitable costs associated with delays.
• Longer time in component selection and qualification

For all of these reasons, small but significant changes in design interpretation and approach have been driving the computing industry to evolve into integrated solutions.

Multi-Chip Approach

Figure 1: View of an 8 mm x 8 mm MLP package for DrMOS proposed by Intel. 
A multi-chip module (MCM) is the integration, within a single package, of any combination of switching devices, controllers, driver ICs and even passive components to form a power train, power subsystem or a stand-alone power system. A few varieties of MCMs are offered and are already used in today’s market, including controllers-plus-drivers-plus-FET combos and FET-plus-Schottky diode co-packaged systems.

Most recently, driver-plus-FET MCMs have gained popularity, particularly in the computing space. This MCM concept has been around for some time. Some fragmented efforts by different semiconductor companies were made in the past to offer these types of products. However, the lack of enthusiasm was due to a mix of average performance, high prices and multiple sourcing considerations. These issues precluded them from the mainstream desktop PC market where cost is by far the definitive reason for adoption.

In an attempt to standardize the few initiatives that were offered and to accelerate market adoption, Intel Corporation defined a product standard called DrMOS (pronounced “driver mos”). This specification defines a set of operational conditions, parameters and dimensions for a standardized driver-plus-FET MCM. It was created in an effort to have a product that meets the tough requirements of modern CPU DC/DC converters. The DrMOS specification has been around for some years now, with the release of the revision 1.0 in November 2004.

Driver-plus-FET MCMs based on the Intel DrMOS specification offer several key benefits:

Improved system efficiency

Several factors contribute to achieving higher efficiency levels in DC/DC conversion systems. In a driver-plus-FET MCM, like the recently released FDMF8700 by Fairchild Semiconductor, internal components are matched thermally, electrically and mechanically. This integration of multiple components in a single chip eliminates parasitic inductances present in layout paths, reducing switching losses particularly at higher frequencies of operation.

Packaging is another factor. The use of a standardized 8 mm x 8 mm molded leadless package (MLP) removes from the system parasitic inductances of packages such as DPAK and SO8, which also reduces switching losses at higher frequencies (Figure 1).

Considerable space savings compared to a discrete approach

Figure 2: A VR11 demo board implementing a new driver-plus-FET MCM. 
By replacing three DPAK devices (one high-side and two low-side FETs) and one SO8-packaged driver IC with one space-efficient 8 mm x 8 mm MLP saves up to 50 percent of space in printer circuit boards (Figure 2). This integrated approach also enables higher frequency of operations; a result that can further save board space since it allows designers to remove passive components such as capacitors and inductors from the printed circuit board.

Easier and faster design.

One of the challenges designers face is matching the right set of drivers and MOSFETs in order to achieve the best possible performance for a given cost boundary. As Figure 3 shows, an efficiency curve can be entirely reshaped depending on the driver IC selection, for a given MOSFET combination. This issue translates into engineering design time and, ultimately, cost that computing manufacturers incur.

Additionally, board layout is dramatically simplified by eliminating all the connection paths among diver IC and FETs and incorporating them more efficiently into a single chip (Figure 4).

Faster component selection and qualification

Figure 3: Effect on efficiency when changing driver ICs with a fixed set of MOSFETs and passive components in a VR11 DC/DC converter system. 
Assuming that a minimum of two suppliers per device is required per OEM standards, in a typical buck converter with one high side and two low side FETs, computing manufacturers need to qualify a total of six part numbers. This includes not only the workload component engineers incur in qualifying six part numbers, but also the time purchasing personnel spend in ensuring that there are no continuity-of-supply issues in six part numbers.

Reduced Total Solution Cost (TSC)

The increasing popularity of driver-plus-FET MCMs provide enormous benefits to computing manufacturers; not only in terms of performance, but also in savings in Total Solution Cost, or TSC. This includes all costs associated with designing and manufacturing a particular application using a specific approach, either discrete- or MCM-based. These costs include, but are not limited to:

• Total BOM cost, including component cost, PCB cost, etc.
• Costs associated to engineering design time.
• Costs in processes for the qualification of multiple part numbers.
• Costs due to capacity impact and equipment time for pick-and-place and testing of multiple devices during the assembly process
• Opportunity costs for missing a target launch date due to delays in design and qualification.

Computing manufacturers who more quickly recognize and identify savings in TSC in their corresponding environments, by going from a discrete-based approach to a driver-plus-FET MCM option will gain a competitive advantage in the market.



Figure 4: A four-phase buck converter circuit based on a newly released driver-plus-FET MCM.  

Looking Ahead

In addition to a common standard such as Intel’s DrMOS spec, a critical point to accelerate adoption is a broad product offering. A top performing Driver Plus FET MCM for a 120A, four-phase DC/DC converter in a server processor core will have much more performance and will be too expensive for a 1.5V DDR buck converter in a desktop PC. Computing designers must look for suppliers that offer broad portfolios with multiple combinations of performance and price points. In doing so, computing manufacturers would reap the benefits of an MCM approach, changing the way power conversion is managed in DC-DC applications. This will mark the "true" dawn of integrated FET plus driver MCMs.

Roberto Guerrero is the WW Segment Manager for Desktops, Servers and Gaming in the Functional Power Group at Fairchild Semiconductor. Before joining Fairchild, Roberto was Product Marketing Manager at ON Semiconductor. Prior to that, he spent seven years at IBM in Latin America working in different roles, from marketing and sales to project management in IBM Global Services. Roberto earned an MBA degree from the University of California at Berkeley. He holds a BSEE degree from the Catholic University of Peru.

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