Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
You can use the Altera1536 FFT/IFFT reference design to accelerate the implementation of 3rd generation partnership project (3GPP) long term evolution (LTE) based wireless networks. 1536 point FFT/IFFT is required at both the basestation and the terminal for the transmission and reception of a 15-MHz carrier. This reference design demonstrates the suitability of Stratix®, Arria®, and Cyclone® series FPGAs for implementing high performance, low latency FFT/IFFT functionality.
Altera supplies the reference design as clear-text Verilog, including a MATLAB bit-accurate simulation model.
- Streaming 1536-point FFT with natural input and output order
- Avalon Streaming (ST) compliant interfaces without backpressure
- Fixed point I/O representation to maintain precision
- 16-bit-wide input data, 33-bit-wide output data
- 16-bit-wide twiddle factor precision
- Transform direction (FFT/IFFT) specifiable on a per-block basis
- Verilog testbench and Tcl script provided for the ModelSim® simulator
- Target clock rate:
- 184.32 MHz for Stratix III devices
- 122.88 MHz for Cyclone III devices