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SyncE-compliant clock touts very low jitter

Wed, 08/14/2013 - 7:10pm

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SyncE-compliant clockSilicon Labs introduced what it claims is the industry’s lowest jitter, lowest power and most frequency-flexible timing solution for high-speed networking equipment based on the Synchronous Ethernet (SyncE) standard. Offering a combination of any-frequency synthesis and desirable jitter performance (as low as 263 fs rms), the new Si5328 precision clock multiplier and jitter attenuator addresses the need for ultra-low jitter physical layer reference clocks in Carrier Ethernet switches and routers. Eighty percent smaller and also 80 percent more power efficient than competing SyncE clocks, according to the company the timing solution is appropriate edge routers, multi-service switches, wireless backhaul systems, DSLAMs and GPON/GEPON optical line termination (OLT) equipment.The Si5328 is fully compliant with ITU-T G.8262 SyncE clock requirements including EEC Options 1 and 2. When paired with a Stratum 3 temperature-compensated crystal oscillator (TCXO), the Si5328 meets all of the jitter, wander and holdover requirements specified by the SyncE standard. With its integrated loop filter featuring selectable loop bandwidths (0.1 Hz and 1 to 10 Hz), the clock can be designed into any networking system that must comply with SyncE specifications. This integration eliminates the need for expensive discrete timing card phase-locked loops (PLLs) in some systems and provides manufacturers the assurance that their networking products can be deployed worldwide by their end customers.

Leveraging Silicon Labs’ patented DSPLL technology, the Si5328 SyncE clock can generate any output frequency ranging from 8 kHz to 808 MHz and from any input frequency from 8 kHz to 710 MHz. This unique frequency-flexible any-rate capability enables networking system designers to synchronize to and generate virtually any legacy telecom or SyncE frequency, simplifying system designs from GbE to 100 GbE. The Si5328 can be digitally reconfigured through I2C or SPI interfaces without the need for costly bill of materials (BOM) changes.

The Si5328 clock’s high level of single-chip integration greatly simplifies printed circuit board (PCB) design. Its DSPLL architecture eliminates the need for external crystal and loop filter components, reducing PCB area while also maximizing immunity to board-level noise. Selectable output signal formats (LVPECL, LVDS, CML and CMOS) ease interfacing with popular Ethernet transceivers and eliminate expensive level shifters and other filtering components. Powered by a single 2.5 or 3.3 V supply, the Si5328 operates without the need for multiple power supplies and discrete filtering required by competing SyncE timing solutions.

Production quantities of Silicon Labs’ SyncE Si5328 clocks are available now in a compact 6 mm x 6 mm QFN package, as well as in two speed grades. The Si5328C-C-GM supports clock outputs up to 346 MHz and is priced at $7.50 (USD) in 10,000-unit quantities. The Si5328B-C-GM supports clock outputs up to 808 MHz and is priced at $9.38 (USD) in 10,000-unit quantities.

Silicon Labs, www.silabs.com

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