Product Releases

PCIe Gen 3 Switches Offer Four On-chip DMA Engines, Multiple NT, SSC, Ports

Mon, 09/19/2011 - 10:31am
PCIe Gen3 switchesPLX Technology, Inc. expanded its PCI Express (PCIe) Gen3 switch family with three new devices compliant with the PCI Express Gen3 r1.0 Specification. The new PLX ExpressLane PEX8749 (48-lanes, 18 ports), PEX8733 (32 lanes, 18-ports) and PEX8725 (24 lanes, 10 ports) PCIe Gen3 switches promise valuable innovation and high port counts to enable new, more powerful designs in servers, storage and communications platforms. Integrated into each new PLX PCIe Gen3 multi-root switch device are two non-transparency (NT) ports, four direct memory access (DMA) engines, two virtual channels (VCs), and up to 12 ports for spread spectrum clock (SSC) isolation. The NT feature enables host failover and redundancy and has been widely used by tier-one OEMs since it was developed in early PCI technology. The on-chip DMA engines enable designers to increase the performance of systems by moving data among endpoints or between memory and endpoints without sacrificing CPU bandwidth. Support for two VCs enable users to prioritize traffic to support desired quality of service (QoS). The SSC clock isolation for each x4 port of the device allows designers to create large systems with each sub-system running its own SSC clock.

In addition to x16 and x8 ports, these switches offer native x2 and x4 ports that enable development of large arrays of SSD based systems with fewer switches. Also included is the support for PCIe specification engineering change notices (ECNs) such as multicast, access control service (ACS), alternative routing-ID interpretation (ARI), atomic operations, and optimized buffer flush/fill (OBFF). PLX PCIe Gen3 devices are fully backwards-compatible with Gen2/Gen1 devices and recommended for all new designs. The PLX Gen3 devices can be used to create Gen3 slots using their bridging capability in a Gen2 platform.

PLX Technology, Inc.



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