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FPGA Family Includes 4 x 3.125 Gbps SRIO

Thu, 05/05/2011 - 6:29am
FPGA familyLattice Semiconductor announced the availability of a 4 x 3.125 Gbps version of the Serial RapidIO 2.1, Level 1 endpoint core using the LatticeECP3 FPGA family. This is an extension of the previously announced SRIO v2.1 core that originally supported 1x and 2x up to 3.125 Gbps and 4x up to 2.5 Gbps. This core can be demonstrated utilizing the industry standard Lattice Advanced Mezzanine Card (AMC) form factor platform. The Serial RapidIO 2.1 IP Core allows for 1x, 2x and 4x lane configurations; supports up to 3.125 Gbps; implements physical layer, transport layer, maintenance transaction handling and error management extensions; provides infrastructure support for external logical layer functions and a choice of how logic layer functions interact with the rest of the system - SoC bus or streaming interfaces; supports software implementations of control plane-oriented functions such as doorbells and messages; and it is backward compatible with the v1.3 specification.

Lattice Semiconductor Corporation
503-268-8000, www.latticesemi.com 
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