Programmable DSP Core Touts Power Efficiency for Next-Gen Communications and Multimedia SoCs
Thu, 09/09/2010 - 10:46am
CEVA, Inc. introduced the CEVA-X1643, a 1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance and portable multimedia. Features include support for an advanced data cache and tightly coupled memory architecture, which streamlines software integration and software porting from other DSP platforms; memory management support simplifying RTOS and multi-tasking; Integrated Power Scaling Unit (PSU), enabling an energy-efficient architecture; configurable 64/128 bit AXI system busses supporting high memory bandwidth; inherent support for seamless migration from TI C6x C-code; and over 1 GHz DSP performance using standard 40nm process technology at worst-case conditions. The CEVA-X1643 DSP features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. With a well-balanced pipeline, the CEVA-X1643 can run at over 1 GHz in chips implemented at the 40 nm technology node.