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WaveFormer Lite Generates Mixed Signal HDL Test Benches for all FPGA Design Flows

Wed, 08/11/2010 - 10:36am
mixed_signal_test_benchSynaptiCAD has just released a major upgrade to WaveFormer Lite, it's entry level tool for generating VHDL and Verilog test benches graphically from timing diagrams drawn by the user. Previously only available as part of the Actel Libero package, WaveFormer Lite can now be purchased directly from SynaptiCAD. WaveFormer Lite generates native VHDL and Verilog testbench code, so it's compatible with all FPGA/ASIC vendors and tool flows without requiring any special runtime engines.

The new version of WaveFormer Lite adds support for displaying analog waveforms, automatically generating analog and digital waveforms from editable waveform block equations, a syntax-coloring editor for VHDL and Verilog, and a new hierarchical project window that enables navigation thru the user's design.

For more information on WaveFormer Lite see the WaveFormer Lite Product Page.

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