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Dynamically Reconfigurable Logic IP Exhibits up to 2x Speed Improvement

Tue, 04/27/2010 - 4:56am

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DRL IPAkya launched its ART2.1, the next generation of its dynamically reconfigurable logic (DRL) IP with several major innovations. According to the company, ART2.1 can run up to twice as fast as its predecessor and will work significantly better with code generated by high-level-language compilers. These characteristics make the IP appropriate for the implementation of high-performance, flexible digital signal processing applications. ART technology separates dataflow circuitry from control logic and provides a large, ready-made library of IP building blocks for designers to work with. It provides two high-level, custom-made design languages; one for data flow and one for control. This IP features a modified configuration instruction pathway, which allows up to 2x system clock speed compared to ART2.0. Its augmented Interconnect Sequencer instruction set is said to improve the performance of code generated by, for example, C compilers.

Akya Limited
44 1757 292626, www.akya.co.uk 
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