With a typical Step Size of 2500 KHz, the CPLL66-3475-3475 PLL/Synthesizer from Crystek operates at 3475 MHz. The PLL/Synthesizer is housed in a 0.6-in. x 0.6-in. x 0.15-in. SMD package, and is programmed using a standard three line interface (Data, Clock and Load Enable). Typical phase noise is -95 dBc/Hz at 10 KHz offset with minimum output power of 3 dBm. VCO voltage is 5 Vdc; PLL voltage is 3 Vdc. Second harmonic suppression is -15 dBc typical.
With a typical Step Size of 2500 KHz, the CPLL66-3475-3475 PLL/Synthesizer from Crystek operates at 3475 MHz. The PLL/Synthesizer is housed in a 0.6-in. x 0.6-in. x 0.15-in. SMD package, and is programmed using a standard three line interface (Data, Clock and Load Enable). Typical phase noise is -95 dBc/Hz at 10 KHz offset with minimum output power of 3 dBm. VCO voltage is 5 Vdc; PLL voltage is 3 Vdc. Second harmonic suppression is -15 dBc typical.
