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Signal Integrity in High-Speed Connectors

Fri, 08/21/2009 - 6:53am

Channel characterization has become a major signal integrity issue,
which is necessitating connector manufactures of high-speed components
to provide comprehensive and empirical SI test data that their equipment performs as specified for the targeted application.

Harting Markus Witte-webThe need for speed is everywhere.  The Internet Protocol has become tremendously important for combining data, voice and video in the same data stream.  Different networks like IMS (Internet Protocol Multimedia Subsystem), VoIP (Voice-over-Internet Protocol), Mobile VoIP, and others use the same protocol for these data packages – referred to as converging networks.  Mobile data services require a higher aggregate bandwidth for network elements like base stations, radio network controllers and core networks, which have to accommodate this increased data traffic.

What started as a gradual trend to higher bit rates accelerated dramatically in 2004, with the introduction by Intel of the PCI-Express standard.  Following this lead, the majority of chip-to-chip connection standards underwent an architectural shift from parallel busses to serializer/deserializer (SERDES) links called "lanes."

With the IP based infrastructure, new standards like the IEEE802.3ap evolved for higher data rates, especially for Ethernet over the backplane assembly.  But, other standards like RapidIO, PCI Express also address higher data rates.  Typical data rates are in the range of 3.125Giga baud per lane and some interconnects already support 10.3125 Giga baud (Gbd) lane rates.  Different protocols are used for the data transport, and each link technology has different requirements for the channel. However, some limits and electrical requirements are defined in the relevant specification. 

While the IEEE802.3ap is in the process to get adopted for new designs, the Ethernet task force is developing the IEEE802.3ba for 40Gb/s and 100Gb/s for future data networks.  Such as AdvancedTCA (Advanced Telecommunications Computing Architecture), the largest specification effort in the history of the PCI Standard (Peripheral Component Interconnect), which is targeted to requirements for the next generation of "carrier grade" communications equipment.  This series of specifications incorporates the latest trends in high-speed interconnect technologies and next-generation processors, promising improved reliability and availability.

But, these advantages of large increases in bit rate come at a cost.  At multi-gigabit per second data rates with channel flight times longer than a bit period, signal integrity is compromised.  High-speed analog effects can impair the signal quality and degrade the bit error rate (BER) of the link.  To ensure optimum performance of high-speed connectors, simulation and characterization analysis needs to be performed – comprehensively and empirically – to establish and adhere to uniform standards.

Channel Characterization
Signal integrity studies the design of high-speed circuits and the accommodation of cleaner signals passing through them.  Cleaner signals, in turn, enable engineers to identify and minimize sources of distortion in data transmission, which could otherwise disrupt timing of the digital logic. 

The ability to effectively transmit a signal is related to the ratio of signal to interference that is presented to the receiver.  Many challenges must be addressed in developing a system where any channel can support transmitting a signal serially at 10Gb/s.  At multi-gigabit/s data rates, link designers must consider reflections at impedance changes, noise induced by densely-packed neighboring connections (crosstalk), and high-frequency attenuation.  Other significant issues of concern for signal integrity that can plague modern digital products and interfere with the detection of the output signal are ringing, ground bounce and power supply noise.

Comprehensive signal integrity tests of connectors in backplane applications have been conducted by HARTING, as well as concurrently supporting sub-standardization committees within PICMG (PCI Industrial Computer Manufacturers Group) and OBSAI (Open Base Station Architecture Initiative).  Standards like IEEE 802.3ap have become relevant and appendix 69B defines the informative limits of the channel.  A confidence level is defined but this is neither normative nor a guarantee that the channel works or does not work without a BER failure. 

It is obviously very challenging to define normative parameters, especially for lane rates beyond 3.125 Gbd due to the need of signal conditioning.  The separation of the channel with defined reference points helps to isolate specific areas of the transmission path.  However, cascading the signal elements later requires careful calibration and de-embedding techniques, especially between the reference transition points.
The PICMG ICCC (Interconnect Channel Characterization Committee) has been challenged to develop a document with ground rules and definitions for channel characterization.  Taking it a step further, and considering the signal propagation path from the cable connector, it becomes even more difficult.  For example, 10 Gigabit/s Small Form Factor Pluggable (SFP+) modules and hosts are well defined within the latest SFF draft specifications with specific electrical requirements and test procedures.

Harting Figure1-webWhile focusing mainly on the physical layer, the transmission of signals between transmitter and receiver can be from chip-to-chip on the same board or chip-to-chip between different boards.  When the signal is between different boards, the physical connection could be a PCB, cable or connector.  The following picture illustrates a data transmission path with an arbitrary assignment of different connector types.

PCB and cable signal traces carry much more current than their on-chip counterparts.  This larger current induces crosstalk primarily in a magnetic, or inductive, mode, as opposed to a capacitive mode. To combat this crosstalk, digital PCB designers must remain acutely aware of not only the intended signal path for every signal, but also the path of returning signal current for every signal. The signal itself and its returning signal current path are equally capable of generating inductive crosstalk.

The measurement of the signal between the chips is not trivial and the test fixture and measurement procedure has a strong impact on the results.  Therefore, a comprehensive documentation with all details of the test fixture and instrument settings is mandatory for the interpretation, reproducibility and comparison of the results.

Harting Figure 2-webThe backplane channel in IEEE802.3ap is defined between Transmitter and Receiver test points TP1 and TP4.

Channel Test and Simulation Parameters
TP1 and TP4 are reference test points in IEEE802.3ap.  Informative channel parameters between these two test points are defined in Annex 69B for 1000BASE-KX @1.25Giga Baud, 10GBASE-KX4 @3.125 Gbd and 10GBASE-KR @10.3125GBd.

Harting Figure 3-web 

Test Parameters:
- Characteristic impedance
- Fitted attenuation
- Insertion loss
- Insertion loss deviation
- Return loss
- Crosstalk
- Power sum differential near-end crosstalk (PSNEXT)
- Power sum differential far-end crosstalk (PSFEXT)
- Power sum differential crosstalk
- Insertion loss to crosstalk ratio (ICR)

Harting Figure 4-webAt these new multi-gigabit/s bit rates, the bit period is shorter than the flight time and echoes of previous pulses can arrive at the receiver on top of the main pulse, and corrupt it.  In signal integrity engineering this is called an eye closure - a reference to the clutter in the center of a type of oscilloscope trace called an eye diagram – representing the results of a simulation driven by a long, multi-cycle sequence, superimposes each bit period over the top of others. 

In IEEE802.3ap the test parameters are informative only and the results do not guarantee that the channel finally works without bit error rates. Other standards like RapidIO or OIF-CEI02.0 agreement use tools like Stateye for compliance testing.  However, the correct measurement of the data is a strong concern in the industry.

Measurement Procedure
The characterization of the passive channel is not Harting Figure 5-webtrivial.  The data transmission through the channel (Figure 1) is very complicated.  The measurement instrument’s cables are terminated with coax connector types like 2.4mm/2.92mm/3.5mm. The access to the component edges is difficult, so four measurement test fixtures are needed.  The test fixture has a strong impact on the results. An error correction is required to remove these effects from the measurement data.  To avoid the rise time degradations and reflections due to the launch connector transition, the use of a high-precision probe (Probe Station) is recommended.

The launch of the connectors for the instrument cables (most likely SMA termination) to the PCB has to be very smooth.   The transition from the board mount coax connector to the PCB trace is optimized with a 3D dynamic field solver.  The production process of the test cards is very critical.  Especially the impedance match of the test fixture, including the connector transition, has to be very accurate.

Harting Figure 6-webScattering (S)-Parameters are measured with a Multiport Vector Network Analyzer.  The S-Parameters can capture the reflection and transmission from junctions in backplanes.  Further, the isolation between signals is important to control in order to avoid interferences caused by adjacent channels.

The data can also be gained with a time domain instrument, while a transformation from the time domain into the frequency domain is required.  The selection of the best suitable software tools and measurement equipment is important to do the channel characterization.  However, the skills of the operator to use the software and test equipment properly is the key for accurate results.

High-Speed Connections Design
As systems are developed to continually support greater high-speed capacities, the design, simulation, measurement and analysis of connectors to optimize channel signal integrity will need to be even more exacting.

The requirements demanded of high-frequency and high speed connections are considerable.  They must be compact, able to withstand hard mechanical knocks, compensate for tolerances between the daughter card and the backplane, while not causing any significant signal reflections and signal attenuation, and must guarantee a reliable contact for at least 15 years.

Such tried and tested connection standards should be expected, and demanded, by both component manufacturers and those that integrate them.  Only in this way can a truly functional mega-gigabit system that supports computing, storage, control, media and packets become widely functional.

Markus Witte, Curriculum Vitae:
Markus Witte has 10 years experience in the connector industry.  He is the Signal Integrity Manager within HARTING Technology Group and responsible for System and Application Management.  Mr. Witte graduated from the University of Applied Sciences, Osnabrueck, Germany in 1998 with a Bachelor of Science in Electrical Engineering.  He has authored and co-authored technical papers for DesignCon, and is supporting sub-standardization groups within PICMG and OBSAI.

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