FPGA Families Support High RLDRAM Rates
The LatticeSC and LatticeSCM FPGA families (collectively, the “LatticeSC/M” families) support RLDRAM I/II rates up to 800 Mbps. The high-speed RLDRAM I and RLDRAM II memory controller IP (intellectual property) is implemented in Lattice’s low-power MACO (Masked Array for Cost Optimization) structured ASIC technology. The FPGAs are fabricated on Fujitsu’s 90 nm CMOS process technology, utilizing 300 mm wafers. Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8 Gbps data rates, PURESPEED parallel I/O with 2 Gbps speed, and FPGA logic operating at 500 MHz.