SerDes Transceiver Offers 30 ps Jitter Performance
Meeting SMPTE 424M jitter specifications, National Semiconductor’s LMH4345 SerDes transceiver exhibits output alignment jitter performance of 30 ps and a minimum input jitter tolerance of 0.6 units interval (UI) in multi-channel broadcast video equipment. The 14 mm² 100-pin TQFP-packaged component includes 4 integrated SDI cable drivers, 2 SDI output drivers, 2 relocked loop-through drivers and a 5-bit differential signaling (LVDS) parallel bus for FPGA interface. The transceiver supports 270 Mbps, 1.485 Gbps and 2.970 Gbps data rates for transmission of digital video broadcasting-asynchronous serial interface, standard-definition, high-definition and the 3G-SDI standard. The device’s 2 receivers include a clock and data recovery circuit (CDR) that automatically detects the incoming serial data rate, extracts the clock and deserializes the data into a 5-bit LVDS stream. The transceiver offers an integrated PLL to clean parallel clock noise, and a typical power consumption of 1.600 W at 3 Gbps. Pricing is $55 in 100 quantities.