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Corelis Offers Free JTAG/Boundary-Scan Training

Mon, 09/29/2008 - 10:09am

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Corelis JTAG/boundary-scan Lasting for 3 days, Corelis gives a free JTAG/boundary-scan training program for clients requiring an introduction and/or review of boundary-scan basics and hands-on experience generating and running tests. In addition to an introduction to boundary-scan, design for boundary-scan testability guidelines and in-system programming strategy are talked about. The test generation and testing methods for boundary-scan-based designs portion explains the generation methodology, execution plan, and interactive debugging concepts of test generation. Afterwards, the training clarifies at-speed embedded functionality testing using an on-board JTAG-based CPU, and in-system programming of CPLDs and Flash memories. Hands-on individual lab exercising using real units under test will teach how to generate and execute interconnect tests; test memory interconnects and logic clusters; use an embedded processor’s JTAG port for embedded functional testing; program CPLDs and Flash memories in circuit; and troubleshoot a test procedure. The seminar is located at their company headquarters in Cerritos, CA.

Corelis, Inc.
562-926-6727, www.corelis.com

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