Featuring second-generation model-based synthesis technology, the DSP Builder Version 8.0 fro Altera, increases productivity for DSP designs by an order of magnitude. This technology allows DSP designers to generate timing-optimized RTL code based on Simulink design descriptions. With this Builder feature, designers can acquire design implementations, running at near-peak FPGA performance, in a matter of minutes. Designing multi-channel signal processing datapaths in applications such as multi-carrier, multi-antenna RF processing in wireless basestations, the Builder technology delivers a variety of productivity. The Builder tool adds pipelined stages and registers, and implements time division multiplexing to generate designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). This version includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.
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