Advertisement
Product Releases
Advertisement

Verification Tool for High Level Synthesis Output Applications

Mon, 01/14/2008 - 6:27am

LISTED UNDER:

Calypto Design Systems announced the availability of SLEC System-HLS for verification of high-level synthesis (HLS) output. Enabling ESL, SLEC (for Sequential Logic Equivalence Checker) formally verifies equivalence between electronic system level (ESL) models and register transfer level (RTL) implementations. SLEC System-HLS tightly integrates SLEC System into HLS design flows by automating setup and supporting HLS language extensions, such as Algorithmic C datatypes from Mentor Graphics and System C Modular Interfaces from Forte Design Systems. This option verifies the RTL code synthesized from system-level models without the need for writing testbenches or running simulation.  LEC System-HLS is included in the recent SLEC 3.0 software release that also increases capacity and optimizes formal algorithms for system-level design styles. Additionally, SLEC 3.0 extends ESL language support beyond the established synthesizable subset. The expanded C/C++ and SystemC language processing capabilities support a wider array of coding constructs, including dynamic memory and arbitrary pointers. Each HLS solution is sold separately and is priced at $50,000 for a one-year, time-based license.

Calypto Design Systems
(408) 850-2300, www.calypto.com

Advertisement

Share this Story

X
You may login with either your assigned username or your e-mail address.
The password field is case sensitive.
Loading