SERDES Framer Interface IP Core Aids Lattice SC/M FPGAs
Using seventeen SERializer/DESerializer (SERDES) channels in the Lattice SC and Lattice SCM (Lattice SC/M) devices, the SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core from Lattice Semiconductor enables the creation of next-generation 40-Gbps systems. LatticeSC/M FPGA devices include 4- to 32-channels of high-speed SERDES capable of supporting data rates from 600 Mbps to 3.8 Gbps, the flexiPCS Physical Coding Sublayer block embedded in the devices supports an array of popular communications data protocols, including SONET/SDH, Gigabit Ethernet, Fibre Channel, 10 Gigabit Ethernet (XAUI), PCI Express and Serial RapidIO. The SFI5 IP solution is available as a downloadable core from the Lattice Semiconductor website.
503-268-8739, www.latticesemi.com