'Pruned' microchips are faster, smaller, and more energy-efficient
"I believe this is the first time someone has taken an integrated circuit and said, 'Let's get rid of the part that we don't need,'" said principal investigator Krishna Palem, the Ken and Audrey Kennedy Professor of Computing at Rice, who holds a joint appointment at Nanyang Technological University (NTU) in Singapore. "What we've shown is that we can boost performance and cut energy use simultaneously if we prune the unnecessary portions of the digital application-specific integrated circuits that are typically used in hearing aids, cameras and other multimedia devices."
Palem, who heads the Rice-NTU Institute for Sustainable and Applied Infodynamics (ISAID), and his collaborators at Switzerland's Center for Electronics and Microtechnology (CSEM) are unveiling the new pruning technique this week in Grenoble, France, at DATE11, the premier European conference on the design, automation and testing of microelectronics.
Pruning is the latest example of "inexact hardware," the key approach that ISAID is exploring with CSEM to produce the next generation of energy-stingy microchips.
The probabilistic concept is deceptively simple: Slash power demands on microprocessors by allowing them to make mistakes. By cleverly managing the probability of errors and by limiting which calculations produce errors, the designers have found they can simultaneously cut energy demands and boost performance.
At DATE11, Rice graduate student Avinash Lingamneni will describe "probabilistic pruning," the novel technique the team created for trimming away the least-used portions of integrated circuits. Lingamneni used the method to create prototype chips at CSEM. The test prototypes contain both traditional circuits and pruned circuits that were produced side by side on the same silicon chip.
"Our initial tests indicate that the pruned circuits will be at least two times faster, consume about half the energy and take up about half the space of the traditional circuits," Lingamneni said. He said he hopes that the system performs even better in the final tests, which are still under way.
Christian Enz, who leads the CSEM arm of the collaboration and is a co-author of the DATE study, said, "The cost for these gains is an 8 percent error magnitude, and to put that into context, we know that many perceptive types of tasks found in vision or hearing applications can easily tolerate error magnitudes of up to 10 percent."
Palem said the next hurdle for "pruning" will be to use the technique to create a complete prototype chip for a specific application. Lingamneni said he hopes to start designing just such a chip for a hearing aid this summer.
"Based on what we already know, we believe probabilistic computing can produce application-specific integrated circuits for hearing aids that can run four to five times longer on a set of batteries than current hearing aids," Palem said. "The collaboration between ISAID and CSEM was key to achieving these results."