TSMC announces 3DIC Chip Technologies using TSVs
The lecture was delivered at the 2010 IEEE International Electron Devices Meeting (IEDM 2010), an international conference on semiconductor manufacturing technologies, which took place from Dec 6 to 8, 2010, in San Francisco, the US.
TSMC prototyped a module by using elemental technologies such as TSV, rewiring layer and micro bump and three-dimensionally stacking semiconductor chips and a 300mm wafer. And the company evaluated its influence on the performances and reliabilities of devices.
TSMC is planning to mass-produce 3D chips by using 28nm and more advanced process technologies. And the company is expected to start volume production within one or two years at the earliest.
"This time, we realized a 3D chip by using our existing technologies and achieved major progress toward volume production," it said.
TSMC said that TSV technologies, design technologies, testing techniques and enough thermal/mechanical strength are important for the volume production of 3D chips. This time, the company delivered the lecture under the theme of TSV technologies, introducing its efforts on elemental technologies to (1) form TSVs, (2) reduce the thickness of a wafer and handle a thin wafer, (3) form a rewiring layer on both sides of a silicon (Si) wafer at low temperatures, (4) form micro bumps and (5) connect a wafer and a chip.
As for (1), TSMC introduced technologies to open a vertical through-hole with a smooth side wall and to prevent copper (Cu) embedded in a through-hole from leaking from the top of the hole (a phenomenon called "Cu extrusion"). The former technology was realized by improving an etching method. Also, by changing the shape of a through-hole, the company prevented Cu from spreading from a through-hole due to a high temperature process. As a result, the leakage current between TSVs were reduced by several digits. Connecting a 300mm wafer and a semiconductor chip.
To develop the latter technology, TSMC analyzed how the phenomenon is related to the plating condition of Cu, grain scale and annealing condition. Before this technology was invented, CMOS layers were damaged by Cu leaked from through-holes on 20% of the chips integrated on 300mm wafers, the company said. This time, TSMC almost completely eliminated this damage by improving the plating condition of Cu, etc.
TSMC evaluated the effectiveness of those 3D stacking technologies by using actual devices. Specifically, it three-dimensionally made an 9 x 2.4mm semiconductor chip on a 300mm CMOS integrated circuit wafer (40-28nm nodes) by using TSVs, rewiring layer, micro bumps, etc.
The pitch of the TSVs was 30μm, and the pitch of the micro bumps that connect the wafer and the chip was 40μm. All of those elemental technologies were realized by using TSMC's existing semiconductor manufacturing technologies.