DSP delivers high performance for processing intensive applications
TI’s new TMDSEVM6457L is an easy-to-use, aggressively priced development tool which includes robust connectivity options such as a breakout card, allowing customers to individually connect certain peripherals to configure the EVM for their needs. The EVM also comes bundled with free software including a copy of TI’s industry leading Code Composer Studio (CCS v4.2) development environment, as well as other production and demonstration software components. By delivering these new low cost, easy-to-use tools and development hardware for high performance DSPs, TI is facilitating access to these devices to a wider range of developers in both existing and emerging applications.
“By offering high value, optimized development solutions at various levels of performance, we are addressing a wider range of developers’ requirements, providing them with tools not previously accessible due to cost and performance constraints,” said Sandeep Kumar, marketing manager of TI’s growth markets and medical business. “TI is listening to and addressing customer needs and developing flexible platforms with a variety of cost and feature options to ease their design processes.”
C6457 key features and benefits
Based on TI’s TMS320C64x+ DSP core, the 850 MHz to 1.2 GHz C6457 delivers 6800 (16-bit) MMACs to 9600 MMACs of peak performance and a cycle for cycle performance improvement of up to 30 percent compared to previous DSP generation.
Performance improvements enabled by 2 MB of on-chip L2 memory (up to 1 MB cacheable), faster 32-bit DDR2 EMIF (667 MHz) and memory, cache and bus architecture enhancements. This gives customers improved cache and memory performance in their designs as well as increased capacity for storing additional data or application features.
High-speed interconnect available with Serial RapidIO (SRIO) and Gigabit Ethernet MAC serializer/deserializer (SERDES) interfaces for efficient inter-processor communications.
On-chip acceleration for wireless applications with two Turbo-Decoder Coprocessors (TCP2) and one Viterbi Coprocessor (VCP2). This offloads the compute intensive Forward Error Correction (FEC) functionality from the DSP core, freeing the DSP for other processing functions and tasks, thus lowering total system cost.
Backwards code compatible with other high performance devices in the C62x and C64x DSP family. This enables legacy code reuse for a significantly shorter development cycle and increased design flexibility.
All TMS320C6457 versions and development toolkits are available for ordering today from TI at www.ti.com/c6457-pr