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The Tinker's Toolbox - TI DAC Boasts Low Power and High Speed

Fri, 05/13/2011 - 7:14am

alixHosted by ECN's Editorial Director, Alix Paultre, the Tinker's Toolbox is the Advantage Design Group's web-based interview show where we talk about the latest technology, components, and design issues for the electronic design engineering community.

philip prattIn this episode, we talk with Philip Pratt of Texas Instruments about their latest 4-channel, 16-bit DAC (digital-to-analog converter). Presented as the industry’s most power-efficient, at 1.25 GSPS, the DAC3484 is 25 percent faster than the next-fastest quad DAC while consuming as little as 250 mW per channel.

 

Here is another link to the podcast: TI Interview DAC

Here is a link to the product presentation slide stack: TI Presentation

 

Here is the press release:

DAC3484 Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced the industry’s most power-efficient 4-channel, 16-bit DAC (digital-to-analog converter). At 1.25 GSPS, the DAC3484 is 25 percent faster than the next fastest quad DAC while consuming as little as 250 mW per channel – 65 percent less than the closest competitor. The DAC3484 is also 40 percent smaller than alternative quad DAC solutions while enabling wideband power amplifier linearization of up to 250 MHz. The wider input bus DAC34H84 or the 2-channel DAC3482 are available to support a linearization bandwidth up to 500 MHz. For more information and to order samples, visit www.ti.com/dac3484-pr.  

“Wireless base station manufacturers are challenged to deliver systems that push the limits of bandwidth and performance while keeping power consumption in check,” said Steve Anderson, senior vice president of TI’s High Performance Analog business. “The DAC3484 and its two related DACs can help customers designing 3G, LTE and WiMAX base stations, wideband repeaters and software defined radios optimize their systems for energy efficiency in a smaller footprint.”  

Key features and benefits

  • 16-bit interleaved 1.25-GSPS input halves the I/O count, reducing FPGA costs and simplifying board routing.
  • 9-mm x 9-mm Multi-row QFN package enables higher-density main and diversity transmitters.
  • Low-jitter 2x to 32x phase locked loop eliminates the need for an external, low-jitter clock multiplier to match the interpolated rate.
  • 2x to 16x interpolation and two independent 32-bit NCOs (numerically controlled oscillators) lower the interface rate and cost of FPGAs, while providing flexibility in frequency planning.
  • Offset, gain, group delay and phase control for system calibration significantly improve sideband suppression for wideband signals when interfacing with IQ modulators, such as the TRF372017, in direct up-conversion radios.
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