Automatic partitioning tool boosts FPGA prototypes’ performance by 10x
Paris, France-based Flexras Technologies has announced its Wasga Compiler, a software tool that boosts multi-FPGA design performance. The company says Wasga Compiler is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. It typically delivers a 10X clock frequency increase, runs fast, handles multi-billion ASIC gates equivalent designs, and maps them to any Altera or Xilinx board, whether it’s off-the-shelf or custom.
Wasga Compiler automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real time. It maximises prototyping system performance and solves hardware/software validation bottlenecks of next generation SoCs to help meet the time-to-market challenges.
“Multi-FPGA platforms are heavily used for ASIC and SoC rapid prototyping. Existing tools notoriously fail the complex partitioning challenge. Verification engineers still rely on a cumbersome manual partitioning methodology,” remarked Hayder Mrabet, Flexras’ CEO. “Wasga Compiler complements FPGA-based SoC prototyping with high performance automatic partitioning. Engineers benefit from high clock frequencies, fast execution time, and unlimited design capacity. Wasga Compiler just makes the multi-FPGA designer’s life easier.”