Magma's Talus IC Implementation System Supports TSMC 28-nm Process Technology through Reference Flow 12.0
"Magma and TSMC have already worked closely to support the design and manufacture of a number of 28-nm ICs for the industry’s highest volume fabless companies,” said Premal Buch, general manager of Magma's Design Implementation Business Unit. "With Talus, Hydra, Tekton, QCP and Quartz DRC, and Reference Flow 12.0, mutual customers can have a high level of confidence in their ability to successfully deliver differentiated ICs using Magma and TSMC solutions."
"Close collaboration with leading EDA vendors such as Magma is critical to delivering the 28-nm design ecosystem,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “Our mutual customers’ silicon successes highlight the effectiveness of TSMC’s process technology and Talus, Hydra, Tekton and Quartz for ICs at 28 nm.”
28-nm Design Enablement Magma's Talus RTL-to-GDSII IC Implementation system supports TSMC 28-nm design rules that have been enhanced in Reference Flow 12.0. Talus' support of Reference Flow 12.0 takes advantage of new power and performance features, providing customers with faster overall design closure and better performance and predictability. In addition, Magma's Quartz DRC and Quartz LVS physical verification tools support in-the-loop physical verification.
At 28 nm and below it becomes increasingly complicated to capture the number of potential variations at all process corners. With Reference Flow 12.0, greater performance is achieved using multiple advanced stage-based on-chip variation (OCV) optimization and analysis tables instead of a single OCV value. This analysis technique is available in Tekton, Magma's standalone static timing analysis tool, and is also supported by Talus Vortex through its MX timing engine. This technique can reduce traditional OCV pessimism and improve performance by removing some of the punitive pessimism associated with traditional OCV modeling.
Reference Flow 12.0 additionally provides significant user margin control through add-on OCV that allows further modeling of voltage and temperature variation and cell-based constraint uncertainty, both of which are supported fully by Talus Vortex and Tekton.
To ensure optimal dummy fill after GDSII stream-out, Reference Flow 12.0 provides for timing criticality information to be passed through to latter stages of the flow, a technique also fully supported by Talus Vortex.
New Low-Power Features TSMC supports both the Common Power Format (CPF) and Unified Power Format (UPF) in Reference Flow 12.0. Talus Power Pro, Magma's advanced low-power optimization technology, also supports both the CPF 1.1 and UPF 2.0 power intent standards. This provides customers with complete flexibility in defining power intent. Talus Power Pro's industry-leading multiple voltage domain (MVdd) infrastructure delivers the most comprehensive power support combined with the simplest use model. In particular, its dynamic voltage and frequency scaling (DVFS) low-power technologies, bolstered by an industry-leading multi-mode, multi-corner framework, enables customers to deliver the maximum performance per watt. These capabilities, combined with Magma's Hydra hierarchical design planner, allow customers to design very large, low-power systems on a chip without sacrificing performance.
To support Reference Flow 12.0, Talus Vortex also delivers optimized cell placement to minimize power hotspots and delivers native electromigration-safe clock placement and network topologies throughout the flow. Talus Vortex with Talus Power Pro now supports post-route multi-mode, multi-corner-aware leakage power optimization through Magma’s Tekton timing analysis tool.
Magma Support for TSMC Reference Flow 12.0
Reference Flow 12.0 is supported by Magma's full RTL-to-GDSII suite of tools, which includes:
• Talus Design – physically aware RTL synthesis
• Talus Vortex – advanced timing and DFM-aware physical implementation
• Talus Power Pro – low-power optimization
• Hydra – hierarchical design planning
• Talus qDRC – timing-aware metal fill
• Quartz DRC – design rule checking
• Tekton – static timing analysis
• QCP – sign-off-quality extraction
Top semiconductor makers worldwide use Magma's electronic design automation (EDA) software to produce chips for electronic applications including tablet computing devices, mobile devices such as smartphones, electronic games, digital video, networking, military/aerospace and memory. Magma products provide the "Fastest Path to Silicon"(tm)and include software for digital design, analog implementation, mixed-signal design, physical verification, circuit simulation, characterization and yield management. The company maintains headquarters in San Jose, Calif., and offices throughout North America, Europe, Japan, Asia and India. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.