The 8-Core Parallax Processor Really Spins 

You will find multi-core chips in servers, workstations and high-end graphics equipment. But you're also likely to find them in games and appliances. A desktop printer, for example, might include a 6-core processor.

The Propeller microcontroller unit (MCU) from Parallax offers a fully deterministic RISC processor with eight 32-bit multiple-instruction multiple-data cores. Each processor--called a cog--has 512 32-bit words of data and program memory and shares it shares with the other cogs 32 kbytes of memory in a central location, called the hub. Every cog has two hardware timers and a video generator that can produce VGA or NTSC/PAL signals. Each cog executes at 20 MIPS or 160 MIPS for the entire chip. Developers can synchronize cogs to achieve higher bandwidths for compute-intensive tasks.

Unlike most MCUs, the Propeller architecture has no interrupts, but because programmers have eight cogs available, essentially they have eight interrupt service routines (ISRs) running concurrently. Instructions cause the processor to halt until a specified time elapses or until an I/O pin changes state. Thus, you can perform interrupt-like operations but without affecting the determinism of the system. There is no operating system or task scheduler to interfere with code timing.

Assembly-language code uses the carry and zero flags to affect the operation of 32 "conditional" instructions, which results in compact code. In addition to programming in assembly language, developers can use Spin, a high-level built-in interpreted language for rapid code development. Parallax plans to have a C compiler available soon for the Propeller.

Propeller developers and Parallax provide royalty-free software libraries under the MIT/X11 license. Each library, called an object, is strongly encapsulated both from a software and a hardware perspective. The encapsulation simplifies integrating new functions into an application and helps eliminate the headache of integrating new code into time-critical applications. www.parallax.com/propeller.

See also: "The Propeller Manual," ver 1.01, Parallax, Inc., Rocklin, CA. 2006. ISBN: 1-928982-38-7.

Virtual Platforms Speed Code Development for Multi-core SoCs

by Larry Lapides. Imperas Ltd. (www.imperas.com)

A funny thing happened on the way to the 100-million-gate system on a chip (SoC). For all its complexity, the greatest cost in creating a product that will use one of these devices comes from software development. According to analyst firm Gary Smith EDA, the cost of software development in 2007 exceeded that of hardware development. Semiconductor companies used to treat software development as an afterthought, but now software defines and differentiates products.

Semiconductor vendors can design and build 100-million-gate SoCs because hardware developers figured out that simulating a design at a high level of abstraction offered more robust verification than gate-level simulation allowed. Register-transfer-level (RTL) simulation has become ubiquitous, and verification tools and methodologies are available for complex IC designs. This high-level simulation verifies proper device functionality before developers commit to silicon. 

For the most part, embedded-system developers test software by running existing data through application code. And the software usually runs on an actual device or on prototype hardware, such as an FPGA-based prototype board.

Virtual platforms, however, provide the equivalent of RTL-simulation technology for embedded software. Thus, developers can simulate software earlier in a design cycle than they could by using hardware prototypes. As software becomes more complex and runs on multi-processor cores in SoCs, developers will require virtual platforms as a way to ensure timely delivery of reliable embedded-systems products.

Many verification techniques and methods developed for hardware design can move directly to the software world. To encourage their wider use for software development, virtual platforms must become easier to use, non-proprietary and interoperable. Fast simulation performance and the capability to support multicore architectures are requirements. Free and open source would help, as well. Today, the Open Virtual Platforms (www.OVPworld.org) group offers free simulation technology that will let embedded-software developers build the infrastructure needed to get embedded systems to level of current.