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Power packaging developments are advancing energy efficiency

Mon, 06/30/2014 - 12:03pm
Mahadevan Iyer2

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Power packaging is an essential part of our design process here at TI.  Our innovative packaging technology brings in advancements in cost, high performance, and low and medium power applications, enabling differentiated products for TI and our customers.  For example, TI recently introduced two flyback power solutions, the UCC28910 and the UCC28630, that achieve the highest energy efficiency and lowest standby power consumption for 5- to 100-watt AC/DC power supplies.  Products like these feature TI’s advanced high voltage and low power packaging solutions, enabling customers to save on energy costs without losing performance.

TI’s power package solutions come in multiple packages like advanced versions of SOIC (for process technologies like LBC7HV) and right now we are supplying our customers with high voltage (and low/medium power) packaging technologies.  On the horizon, I see increasing applications that would necessitate high voltage/high power/high speed devices for market segments like industrial and building automation, energy generation and distribution, and automotive.  Multi-chip modules/system in package technologies will enhance package and system level integration for these applications.

Energy efficiency is a critical requirement for a number of applications today, as well as for those to come – everything from automotive and industrial technologies to consumer products.  By 2040, total electricity demand will grow by a whopping 29 percent, leading to things like increased greenhouse gases and carbon footprint.  Some of this can be reduced through more efficient power conversion in semiconductor products, especially wide-bandgap (WBG) devices.  To enable the higher energy efficiency and increased power density (reduced footprint) with WBG, the devices need to be switched at much higher speed and/or run at temperatures higher than you would with Si.  This requires packages with low parasitics, increased thermal efficiency and multi-chip packaging solutions.  The efficient power conversion capability of WBG devices coupled with the higher thermal efficiency of the package would enable energy efficient power conversion systems.

We know that packaging can contribute to energy efficiency, but what are some challenges that packaging technologists and assembly manufacturing engineers need to consider to get there?

Packaging design optimization by modeling and characterization is a key factor in the design and development of energy efficient power packaging solutions. For example, device heat dissipation and thermal efficiency necessitates innovative designs and application of materials, and there have been many recent thermal management developments at the package level to address this.  Size/form factor is also very important, especially in applications such as wearables and medical devices.  Packages like quad flat no-lead (QFN), and other leadframe-based packages like SOIC, PDIP, TSOP and TO are popular solutions for power packages.

Silicon/package interfaces, materials for high performance (high voltage, high power, high temperature, etc.) all need to be carefully selected and characterized for different electrical, thermal and reliability/mechanical requirements. These power packages will also find applications in automotive, an industry with some of the most stringent reliability requirements out there.  A robust and cost effective manufacturing capacity and supply chain are also equally important for these long lasting applications.

If you’d like to hear more about the latest packaging design challenges and trends, make sure to stop by the TechXPOTs at this year’s SEMICON West:
Driving Automotive Innovation: The Enabling Role of Semiconductor and IC Packaging
Lance Wright, Manager, Analog Packaging Materials and High Reliability
Wednesday, July 9 from 2:45 – 3:10 pm, North Stage, North Hall, Moscone Center
 
Silicon and Packaging Integration: Enabling Power Wideband Gap Device Performance
Dr. Sameer Pendharkar, TI Fellow and High Voltage roadmap manager
Thursday, July 10 from 11:50 am – 12:10 pm, North Stage, North Hall, Moscone Center

This post originally published on TI’s Power House blog.

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