EnSilica launches version 2.5 of its eSi-RISC Development Suite
EnSilica has launched the eSi-RISC Development Suite v2.5, a new version of its complete development environment for evaluating the EnSilica family of eSi-RISC highly configurable and low-power soft processor cores and the development of embedded applications. The eSi-RISC Development Suite v2.5 features new capabilities for multicore support, significantly enhanced compiler performance and ultra low-power applications support.
With the increasing trend towards multicore eSi-RISC designs such as dual core secure processor applications and Posedge’s innovative 7-core Residential and SMB Gateway, the eSi-RISC development Suite v2.5 now provides JTAG debug and control over all processors in the JTAG chain. In addition, optional load locked and store conditional instructions have been added to the instruction set to support multicore systems.